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1 of 130 rev: 103008 note: some revisions of this device may incor porate deviations from published specifications known as erra ta. multiple revisions of any device may be simultaneously available through various sales channel s. for information about device errata, click here: www.maxim-ic.com/errata . + general description the ds32506 (6 port), ds32508 (8 port), and ds32512 (12 port) line interface units (lius) are highly integrated, low-power, feature-rich lius for ds3, e3, and sts-1 applications. each liu port in these devices has independent receive and transmit paths, a jitter attenuator, full-featured pattern generator and detector, performance-monitoring counters, and a complete set of loopbacks. an on- chip clock adapter generates all line-rate clocks from a single input clock. ports are independently software configurable for ds3, e3, and sts-1 and can be individually powered down. control interface options include 8-bit parallel, spi?, and hardware mode. applications sonet/sdh and pdh multiplexers digital cross- connects access concentrators atm and frame relay equipment csus/dsus pbxs wan routers and switches dslams functional diagram features pin-compatible family of products each port independently configurable receive clock and data recovery for up to 457 meters (1500 feet) of 75 coaxial cable standards-compliant transmit waveshaping uses 1:1 transformers on both tx and rx three control interface options: 8/16-bit parallel, spi, and hardware mode jitter attenuators (one per port) can be placed in the receive path or the transmit path jitter attenuators have provisionable buffer depth: 16, 32, 64, or 128 bits built-in clock adapter generates all line-rate clocks from a single input clock (ds3, e3, sts-1, 12.8mhz, 19.44mhz, 38.88mhz, 77.76mhz) per-port programmable internal line termination requiring only external transformers high-impedance tx and rx, even when v dd = 0, enables hot-swappable, 1:1 and 1+1 board redundancy without relays per-port bert for prbs and repetitive pattern generation and detection tx and rx open and short detection circuitry transmit driver monitor circuitry receive loss-of-signal (los) monitoring compliant with ansi t1.231 and itu g.775 automatic data squelching on receive los large line code performance-monitoring counters for accumulation intervals up to 1s local and remote loopbacks transmit common clock option power-down capability for unused ports low-power 1.8v/3.3v operation (5v tolerant i/o) industrial temperature range: -40c to +85 c small package: 23mm x 23mm, 484-pin bga ieee 1149.1 jtag support ordering information part lius temp range pin-package ds32506 6 0c to +70c 484 bga ds32506n 6 -40c to +85c 484 bga ds32508 8 0c to +70c 484 bga ds32508n 8 -40c to +85c 484 bga ds32512 12 0c to +70c 484 bga ds32512n 12 -40c to +85c 484 bga note: add the + suffix for the lead-free package option. ds32506/ds32508/ds32512 6-/8-/12-port ds3/e3/sts-1 liu www.maxim-ic.com receive clock a nd data dallas semiconductor ds325xx clk data clk data transmit clock a nd data control a nd status txp txn rxp rxn each liu line in ds3, e3, or sts-1 line out ds3, e3, or sts-1 downloaded from: http:///
ds32506/ds32508/ds32512 2 of 130 table of contents 1. standards compli ance ............................................................................................. 6 2. block di agram .............................................................................................................. 7 3. application example .................................................................................................. 8 4. detailed d escription.................................................................................................. 9 5. detailed featur es..................................................................................................... 11 5.1 g lobal f eatures ....................................................................................................................... 11 5.2 r eceiver ..................................................................................................................................... 11 5.3 t ransmitter ............................................................................................................................... 11 5.4 j itter a ttenuator ..................................................................................................................... 11 5.5 b it e rror -r ate t ester (bert) f eatures ............................................................................... 12 5.6 c lock a dapter ........................................................................................................................... 12 5.7 p arallel m icroprocessor i nterface f eatures ..................................................................... 12 5.8 spi s erial m icroprocessor i nterface f eatures .................................................................. 12 5.9 m iscellaneous f eatures .......................................................................................................... 12 5.10 t est f eatures ............................................................................................................................ 12 5.11 l oopback f eatures ................................................................................................................... 12 6. control interf ace modes...................................................................................... 13 7. pin descri ptions ......................................................................................................... 14 7.1 s hort p in d escriptions ............................................................................................................ 14 7.2 d etailed p in d escriptions ........................................................................................................ 17 8. functional description .......................................................................................... 24 8.1 liu m ode .................................................................................................................................... 24 8.2 t ransmitter ............................................................................................................................... 24 8.2.1 transmit clock ................................................................................................................. ................... 24 8.2.2 framer interface format and the b3zs/hdb 3 encoder..................................................................... 24 8.2.3 error inse rtion ..................................................................................................................................... 24 8.2.4 ais gener ation................................................................................................................. ................... 25 8.2.5 waveshaping .................................................................................................................... .................. 25 8.2.6 line build -out ..................................................................................................................................... 25 8.2.7 line dr iver.................................................................................................................... ....................... 25 8.2.8 interfacing to the line ........................................................................................................ ................. 25 8.2.9 driver monitor and output failure detection .................................................................................... .. 26 8.2.10 power- down..................................................................................................................... ................... 26 8.2.11 jitter generation (intrinsic).................................................................................................................. 26 8.2.12 jitter transfer ................................................................................................................ ...................... 26 8.3 r eceiver ..................................................................................................................................... 30 8.3.1 interfacing to the line ........................................................................................................ ................. 30 8.3.2 optional preamp ................................................................................................................ ................. 30 8.3.3 automatic gain control (a gc) and adaptive equalizer ..................................................................... 30 8.3.4 clock and data re covery (cdr) .................................................................................................. ...... 31 8.3.5 loss-of-signal (l os) detector.................................................................................................. .......... 31 8.3.6 framer interface format and the b3zs/hdb 3 decoder .................................................................... 32 8.3.7 power- down..................................................................................................................... ................... 33 8.3.8 input failure detection........................................................................................................ ................ 33 8.3.9 jitter and wander tolerance.................................................................................................... ........... 34 8.3.10 jitter transfer ................................................................................................................ ...................... 35 8.4 j itter a ttenuator ..................................................................................................................... 35 8.5 bert........................................................................................................................................... 36 downloaded from: http:///
ds32506/ds32508/ds32512 3 of 130 8.5.1 configuration and monito ring................................................................................................... ........... 36 8.5.2 receive pattern detection ...................................................................................................... ............ 37 8.5.3 transmit pattern generation.................................................................................................... ........... 39 8.6 l oopbacks .................................................................................................................................. 40 8.7 g lobal r esources .................................................................................................................... 40 8.7.1 clock rate a dapter (c lad)................................................................................................................ 40 8.7.2 one-second refere nce generator ................................................................................................. .... 41 8.7.3 general-purpos e i/o pins....................................................................................................... ............ 42 8.7.4 performance monitor register update ............................................................................................ ... 42 8.7.5 transmit manual e rror insertion ................................................................................................ ......... 43 8.8 8-/16-b it p arallel m icroprocessor i nterface ...................................................................... 43 8.8.1 8-bit and 16-bit bus widths .................................................................................................... ............ 43 8.8.2 byte sw ap mode ................................................................................................................. ................ 43 8.8.3 read-write and da ta strobe modes ............................................................................................... ... 43 8.8.4 multiplexed and nonmul tiplexed operation ....................................................................................... . 43 8.8.5 clear-on-read and cl ear-on-write modes ....................................................................................... 44 8.8.6 global write mode .............................................................................................................. ................ 44 8.9 spi s erial m icroprocessor i nterface ................................................................................... 44 8.10 i nterrupt s tructure ................................................................................................................ 46 8.11 r eset and p ower -d own ............................................................................................................ 47 9. register maps and descript ions......................................................................... 49 9.1 o verview .................................................................................................................................... 49 9.1.1 status bits .................................................................................................................... ....................... 49 9.1.2 configurati on fields ........................................................................................................... ................. 49 9.1.3 counters....................................................................................................................... ....................... 49 9.2 o verall r egister m ap .............................................................................................................. 50 9.3 g lobal r egisters ...................................................................................................................... 51 9.4 p ort c ommon r egisters .......................................................................................................... 62 9.5 liu r egisters ............................................................................................................................ 70 9.6 b3zs/hdb3 e ncoder r egisters .............................................................................................. 79 9.7 b3zs/hdb3 d ecoder r egisters .............................................................................................. 80 9.8 bert r egisters ........................................................................................................................ 84 10. jtag info rmation ................................................................................................... 91 11. electrical ch aracteris tics ............................................................................. 92 12. pin assign ments.................................................................................................... 106 13. package in formation......................................................................................... 127 13.1 484-l ead bga (23 mm x 23 mm ) (56-g60038-001) ..................................................................... 127 14. thermal in formation ......................................................................................... 128 15. acronyms and a bbreviat ions......................................................................... 129 16. trademark ackn owledgem ents.................................................................... 129 17. data sheet revisi on history ........................................................................... 130 downloaded from: http:///
ds32506/ds32508/ds32512 4 of 130 list of figures figure 2-1. bl ock diagram ...................................................................................................... ..................................... 7 figure 3-1. 12-port unch annelized ds3/ e3 card .................................................................................. ..................... 8 figure 4-1. external connections, internal terminati on enabled................................................................. ............... 9 figure 4-2. external connections, internal termi nation disabled................................................................ ............. 10 figure 8-1. ds3 wa veform template .............................................................................................. .......................... 27 figure 8-2. sts-1 wa veform template............................................................................................ ......................... 28 figure 8-3. e3 wa veform template............................................................................................... ............................ 29 figure 8-4. sts-1 and e3 jitter to lerance...................................................................................... .......................... 34 figure 8-5. ds3 ji tter tolerance............................................................................................... ................................. 34 figure 8-6. ds3 and e3 wander to lerance ........................................................................................ ...................... 35 figure 8-7. jitter att enuation/jitter transfer ................................................................................. ............................. 36 figure 8-8. prbs synchron ization stat e diagr am................................................................................. ................... 38 figure 8-9. repetitive pattern synchronization st ate diag ram................................................................... .............. 39 figure 8-10. spi clock pola rity and phas e options.............................................................................. .................... 45 figure 8-11. spi bu s transactions.............................................................................................. .............................. 46 figure 8-12. interr upt signal flow ............................................................................................. ................................ 47 figure 11-1. transmitter framer interface timi ng diagram....................................................................... ............... 95 figure 11-2. receiver framer interface ti ming diag ram .......................................................................................... 95 figure 11-3. parallel cpu interface intel read timing diagram (nonmultiplexed) ................................................. . 99 figure 11-4. parallel cpu interface intel write timing diagram (nonmultiplexed) ................................................ .. 99 figure 11-5. parallel cpu interface motorola read timing diagra m (nonmult iplexed) ......................................... 100 figure 11-6. parallel cpu interface motorola write timing diagra m (nonmult iplexed) ......................................... 100 figure 11-7. parallel cpu interface inte l read timing diagr am (multi plexed) .................................................... ... 101 figure 11-8. parallel cpu interface inte l write timing diagr am (multiplexed) ................................................... .... 101 figure 11-9. parallel cpu interface motoro la read timing diag ram (multiplexed)................................................ 102 figure 11-10. parallel cpu interface motoro la write timing diag ram (multiplexed).............................................. 102 figure 11-11. spi interf ace timing diagram ..................................................................................... ...................... 104 figure 11-12. jtag timing diagram.............................................................................................. ......................... 105 figure 12-1. ds32512 pin assignment, hard ware and microprocessor interfaces................................................ 109 figure 12-2. ds32512 pin assignm ent, hardware in terface only ................................................................... ....... 111 figure 12-3. ds32512 pin assignmen t, microprocessor interface only ............................................................. .... 113 figure 12-4. ds32508 pin assignment, hard ware and microprocessor interfaces................................................ 115 figure 12-5. ds32508 pin assignm ent, hardware in terface only ................................................................... ....... 117 figure 12-6. ds32508 pin assignmen t, microprocessor interface only ............................................................. .... 119 figure 12-7. ds32506 pin assignment, hard ware and microprocessor interfaces................................................ 121 figure 12-8. ds32506 pin assignm ent, hardware in terface only ................................................................... ....... 123 figure 12-9. ds32506 pin assignmen t, microprocessor interface only ............................................................. .... 125 downloaded from: http:///
ds32506/ds32508/ds32512 5 of 130 list of tables table 1-1. applicable te lecommunication s standards ............................................................................. .................. 6 table 7-1. short pin descriptions .............................................................................................. ................................ 14 table 7-2. analog line in terface pin de scriptions .............................................................................. ...................... 17 table 7-3. digital framer interface pin descriptions........................................................................... ...................... 17 table 7-4. global pin descri ptions ............................................................................................. ............................... 18 table 7-5. hardware inte rface pin de scriptions................................................................................. ....................... 19 table 7-6. parallel inte rface pin de scriptions ................................................................................. .......................... 21 table 7-7. spi serial in terface pin de scriptions ............................................................................... ........................ 22 table 7-8. clad pin descriptions ............................................................................................... .............................. 22 table 7-9. jtag pin descr iptions ............................................................................................... .............................. 23 table 7-10. power-su pply pin de scriptions ...................................................................................... ........................ 23 table 7-11. manufacturing test pin de scriptions................................................................................ ...................... 23 table 8-1. jitte r generation ................................................................................................... .................................... 26 table 8-2. ds3 wa veform equations .............................................................................................. .......................... 27 table 8-3. ds3 waveform test parameters and limits ............................................................................. ............... 27 table 8-4. sts-1 wa veform equations ............................................................................................ ......................... 28 table 8-5. sts-1 waveform test paramete rs and li mits......................................................................................... 28 table 8-6. e3 waveform test parameters and limits.............................................................................. ................. 29 table 8-7. transformer characteristics ......................................................................................... ............................ 30 table 8-8. recomm ended transformers............................................................................................ ....................... 30 table 8-9. pseudorandom pattern ge neration..................................................................................... ..................... 37 table 8-10. repetitive pattern ge neration ................................................................................................................ 37 table 8-11. clad cloc k source settings ......................................................................................... ........................ 41 table 8-12. clad cloc k pin output settings..................................................................................... ....................... 41 table 8-13. global one-se cond refere nce source................................................................................. ................. 41 table 8-14. gpio pin global signal as signment s .................................................................................................... 42 table 8-15. gpio pin control................................................................................................... ................................. 42 table 8-16. reset and power-down sources ....................................................................................... .................... 48 table 9-1. overa ll register map................................................................................................ ................................ 50 table 9-2. port registers...................................................................................................... ..................................... 50 table 9-3. global register map................................................................................................. ................................ 51 table 9-4. port co mmon register map............................................................................................ ......................... 62 table 10-1. jt ag id code ....................................................................................................... ................................. 91 table 11-1. recommended dc operating conditions ................................................................................ .............. 92 table 11-2. dc ch aracteristics................................................................................................. ................................. 93 table 11-3. framer interface timing ............................................................................................ ............................. 94 table 11-4. receiver input char acteristicsds3 and sts-1 modes................................................................. ...... 96 table 11-5. receiver input characteristic se3 mode ............................................................................. ................ 96 table 11-6. transmitter output c haracteristicsds3 and sts-1 modes............................................................. ... 97 table 11-7. transmitter output characteristicse3 mode......................................................................... .............. 97 table 11-8. parallel cp u interfac e timing ...................................................................................... .......................... 98 table 11-9. spi in terface timing ............................................................................................... .............................. 103 table 11-10. jtag interface timing............................................................................................. ........................... 105 table 12-1. pin assignments sorted by signal name for ds 32506/ds32508/ ds32512 ....................................... 106 table 14-1. thermal proper ties, natural convection ............................................................................. ................. 128 table 14-2. theta-ja ( ja ) vs. ai rflow.................................................................................................................. .... 128 downloaded from: http:///
ds32506/ds32508/ds32512 6 of 130 1. standards compliance table 1-1. applicable te lecommunications standards specification specification title ansi t1.102-1993 digital hierarchyelectrical interfaces t1.231-2003 digital hierarchylayer 1 in-service di gital transmission performance monitoring t1.404-2002 network-to-customer inst allationds3 metallic interface specification at&t tr54014 accunet? t45 service description and interface specification, 05/92 etsi en 300 686 business telecommunications; 34mbps and 140mbps digital leased lines (d34u, d34s, d140u, and d140s); netw ork interface presentation, v1.2.1 february 2001 en 300 687 business telecommunications; 34mbps digital leased lines (d34u and d34s); connection characteristics , v1.2.1 february 2001 en 300 689 access and terminals (at); 34mbps digital leased lines (d34u and d34s); terminal equipment interface, v1.2.1july 2001 tbr 24 business telecommunications; 34mbps digital unstructured and structured lease lines; attachment requirements for terminal equipment interface , july 1997 itu-t g.703 physical/electrical characteristics of hierarchical digital interfaces, n ovember 2001 g.751 digital multiplex equipment operating at the third-order bit rate of 34,368kbps and the fourth-order bit rate of 139,264kbps and using positive justification, n ovember 1988 g.755 digital multiplex equipment operating at 139,264 kbit/s and multiplexing three tributaries at 44,736 kbit/s , n ovember 1988 g.775 loss of signal (los) and alarm indication si gnal (ais) defect detection and clearance criteria , n ovember 1994 g.823 the control of jitter and wander within digital networks that are based on the 2048kbps hierarchy , march, 2000 g.824 the control of jitter and wander within digital networks that are based on the 1544kbps hierarchy , march, 2000 o.151 error performance measuring equipment operating at the primary rate and above , october 1992 o.161 in-service code violation monitors for digital systems , n ovember 1988 o.152 equipment to perform in-service monitoring on 2048, 8448, 34,368 and 139,264 kbit/s signals , october 1992 telcordia gr-253-core sonet transport systems: common generic criteria , issue 3, september 2000 gr-499-core transport systems generic requirements (tsgr): common requirements, issue 2, december 1998 gr-820-core generic digital transmission surveillance , issue 2, december 1997 downloaded from: http:///
ds32506/ds32508/ds32512 7 of 130 2. block diagram figure 2-1. block diagram jtag rlos n agc, equalizer, and cdr wave- shaping ja rxp n rxn n txp n txn n alb b3zs/ hdb3 decoder b3zs/ hdb3 encoder pattern detector pattern generator dlb llb ais generator rpos n / rdat n rclk n rneg n / rlcv n tpos n / tdat n tclk n tneg n clad parallel and spi bus interfaces hw ifsel[2:0] cs wr / r/ w rd / ds ale a[10:1] d[5:3] cpha / d[6] cpol / d[7] sclk / d[2] sdi / d[1] sdo / d[0] int hiz rdy / ack port n (1 of 12) refclk cladbyp clka clkb clkc clkd rbin rmon n tlbo n jas[1:0] tbin tais n lm n [1:0] gpioa n gpiob n lb n [1:0] rclki tclki tcc d[15:8] bswap / a[0] test jtrst jtclk jtms jtdi jtd0 ares line driver toe n pre-amp driver monitor tdm n jad[1:0] lbs tpd rpd aist rst dallas semico n ductor ds325xx downloaded from: http:///
ds32506/ds32508/ds32512 8 of 130 3. application example figure 3-1. 12-port unchannelized ds3/e3 card 77.76mhz telecom bus ds31912 12-port ds3/e3/sts-1 mapper ds32512 12-port ds3/e3/sts-1 liu downloaded from: http:///
ds32506/ds32508/ds32512 9 of 130 4. detailed description the ds32506 (6 port), ds32508 (8 port), and ds32512 (12 port) lius perform the functions necessary for interfacing at the physical layer to ds3, e3, or sts-1 lines. each liu has independent receive and transmit paths and a built-in jitter attenuator. the receiver performs clock and data recovery from a b3zs- or hdb3-coded alternate mark inversion (ami) signal and monitors for lo ss of the incoming signal. the receiver optionally performs b3zs/hdb3 decoding and outputs the recovered data in either binary (nrz) or digital bipolar format. the transmitter accepts data in either bina ry (nrz) or digital bipolar format, optionally performs b3zs/hdb3 encoding, and drives standard pulse-shape waveforms onto 75 coaxial cable. both transmitter and receiver are high- impedance when v dd is out of spec to enable hot-swappable 1:1 and 1+1 board redundancy without relays. the jitter attenuator can be mapped into the receiver data pat h, mapped into the transmitter data path, or disabled. an on-chip clock adapter generates all line-rate clocks from a single input clock. control in terface options include 8- or 16-bit parallel, spi, and hardware mode. the ds325xx lius c onform to the telecommunications standards listed in table 1-1 . the external components required for proper operation are shown in figure 4-1 and figure 4-2 . figure 4-1. external connections , internal termination enabled txp txn rxp rxn 1.8v power plane ground plane tvdd rvdd jvdd tvss rvss jvss 0.01 f 0.1 f 1 f 0.01 f 0.1 f 1 f 0.01 f 0.1 f 1 f 1:1 1:1 txp txn downloaded from: http:///
ds32506/ds32508/ds32512 10 of 130 figure 4-2. external connections , internal termination disabled txp txn rxp rxn 1.8v power plane ground plane tvdd rvdd jvdd tvss rvss jvss 0.01 f 0.1 f 1 f 0.01 f 0.1 f 1 f 0.01 f 0.1 f 1 f 1:1 42.2 (1%) 0.05 f 42.2 (1%) 1:1 38.3 (1%) txp txn 0.05 f 38.3 (1%) shorthand notations. the notation ds325xx throughout this data s heet refers to either the ds32506, ds32508, or ds32512. this data sheet is the specification for all three devices. the lius on the ds325xx devices are identical. for brevity, this document uses the pin nam e and register name shorthand namen, where n stands in place of the liu port number. for ex ample, on the ds32506, tclkn is shorthand notation for pins tclk1, tclk2, tclk3, tclk4, tclk5 and tclk6 on liu po rts 1, 2, 3, 4, 5 and 6, respective ly. this document also uses generic pin and register names such as tclk (without a number su ffix) when describing liu operation. when working with a specific liu on the ds325xx devices, generic names like tclk should be converted to actual pin names, such as tclk1. downloaded from: http:///
ds32506/ds32508/ds32512 11 of 130 5. detailed features 5.1 global features three interface modes: hardware, 8-/16-bit parallel bus, and spi serial bus independent per-port operation (e.g., line rate, jitter attenuator placement, or loopback type) clock, data, and control signals can be inverted to allow a glueless interface to other devices manual or automatic one-second update of performance monitoring counters each port can be put into a low-power standby mode when not being used requires only a single reference clock for all three liu data rates using internal clock rate adapter jitter attenuators can be used in either transmit or receive path detection of loss-of-transmit clock two programmable i/o pins per port optional global write mode configures all lius at the same time glueless interface to neighboring framer and mapper components 5.2 receiver agc/equalizer block handles from 0 to 22db of cable loss programmable internal termination resistor loss-of-lock (lol) pll status indication interfaces directly to a dsx monitor signal (~20db flat loss) using built-in preamp digital and analog loss-of-signal (los) detector s (compliant with ansi t1.231 and itu g.775) software programmable b3zs/hdb3 or ami decoding detection and accumulation of bipolar violations (bpv), code violations (cv), and excessive zeros occurrences (exz) detection of receipt of b3zs/hdb3 codewords binary or bipolar framer interface on-board programmable prbs detector per-channel power-down control 5.3 transmitter standards-compliant waveshaping programmable waveshaping programmable internal termination resistor binary or bipolar framer interface gapped clock capable up to 78mhz with jitter attenuator in transmit path wide 50 20% transmit clock duty cycle transmit common clock option software programmable b3zs/hdb3 or ami decoding programmable insertion of bipolar violations (bpv), code violations (cv), and excessive zeros (exz) ais generator: unframed all ones, framed ds3 ais, and sts-1 ais-l line build-out (lbo) control high-impedance line-driver output mode to support protection-switching applications per-channel power-down control output driver monitor 5.4 jitter attenuator one jitter attenuator per port fully integrated, requires no external components meets all applicable ansi, itu, etsi, and telcordia jitter transfer and output jitter requirements can be placed in the transmit path, receive path or disabled programmable fifo depth: 16, 32, 64, or 128 bits overflow and underflow status indications downloaded from: http:///
ds32506/ds32508/ds32512 12 of 130 5.5 bit error-rate t ester (bert) features one bert per port software programmable for insertion toward the transm it line interface or the receive system interface generates and detects pseudo-random patterns of length 2 n - 1 (n = 1 to 32) and repetitive patterns from 1 to 32 bits in length large 24-bit error counter and 32-bit bit counter allows testing to proceed for long periods without host intervention errors can be inserted in the generated bert patterns for di agnostic purposes (single bit errors or specific bit- error rates) pattern synchronization even in the presence of 10 -3 bit-error rate 5.6 clock adapter creates ds3, e3, sts-1, and/or telecom bus clocks from single input reference clock input reference clock can be ds3, e3, sts-1, 12.8mhz, 19.44mhz, 38.88mhz, or 77.76mhz use of common system timing frequencies such as 19. 44mhz eliminates the need for any local oscillators, reducing cost and board space very small jitter gain and intrinsic jitter generation derived clocks can be output for external system use transmit signals using clad clocks meet telcordi a (ds3) and itu (e3) jitter and wander requirements 5.7 parallel microprocessor interface features multiplexed or nonmultiplexed 8- or 16-bit interface configurable for intel mode ( cs , wr , rd ) or motorola mode ( cs , ds , r/w ) ready ( rdy/ack ) handshake output signal 5.8 spi serial micropr ocessor interface features operation up to 10mbps burst mode for multibyte read and write accesses programmable clock polarity and phase half-duplex operation gives option to tie sdi and sdo together externally to reduce wire count 5.9 miscellaneous features global reset input pin global interrupt output pin two programmable i/o pins per port 5.10 test features five pin jtag port all functional pins are in-out pins in jtag mode standard jtag instructions: sample/preload, bypass, extest, clamp, highz, idcode hiz pin to force all digital output and i/o pins into a high-impedance state test pin for manufacturing test modes 5.11 loopback features analog local loopbackalb (transmit line output to receive line input) diagnostic local loopbackdlb (transmit framer interface to receive framer interface) line loopbackllb (receive clock and data recover to transmit waveshaping) optional ais generation on the line side of the loopback during diagnostic loopback downloaded from: http:///
ds32506/ds32508/ds32512 13 of 130 6. control in terface modes the ds325xx devices can be controlled by hardware interface, by mi croprocessor interface, or by a combination of both interfaces at the same time. the hardware interfac e is configured (enabled or disabled) independently from the microprocessor interface (8-bit parallel, 16-bit parallel, spi, or disabled). when the hardware interface is enabled ( hw = 1), device configuration can be controlled by input pins, while device status can be sensed on output pins. when the hardware interface is disabled ( hw = 0), all the pins in table 7-5 are disabled (inputs are ignored; outputs are placed in a high-impedance state). the microprocessor interface provides access to features, configuration options, and device status information that the hardware interface does not support. the micropro cessor interface is enabled and configured by the ifsel pins. when ifsel = 01x, the spi serial interface is ena bled. when ifsel = 10x, the 8-bit parallel interface is enabled. when ifsel = 11x, the 16-bit parallel interface is enabled. for both the 8- and 16-bit parallel interfaces, ifsel[0] = 0 specifies an intel-style bus ( cs , rd , and wr control signals) while ifsel[0] = 1 specifies a motorola- style bus ( cs , r/w , and ds control signals). through the microprocesso r interface an external microprocessor can access a set of internal configuration and status registers inside the device. pins that are not used by the selected microprocessor interface type but are used in other microprocessor interface modes are disabled (inputs are ignored and considered to be low and can be left floati ng or wired low or high; outputs are placed in a high- impedance state and can be left unconnected or wired low or high). when no microprocessor interface is selected (ifsel = 000) all microprocessor interf ace inputs are ignored, and all micropro cessor interface outputs are put in a high impedance state. when both the hardware interface and the microprocessor interface are enabled at the same time, many internal settings of the device can be configured by both a hardware interface pin and a microprocessor interface register bit with identical names and functions. in this situation t he actual internal device setting is the logical or of pin assertion and register bit assertion. for example, the transmitter output driver is enabled when the toe pin is high or the toe register bit is high. when both the hardware interface and the microprocessor interface are enabled at the same time, the following hardware interface pins are i gnored and replaced by equivalent configuration register fields: lmn[1:0] , jas[1:0] , jad[1:0] , lbn[1:0] , and lbs . downloaded from: http:///
ds32506/ds32508/ds32512 14 of 130 7. pin descriptions note: all digital pins are i/o pins in jtag mode. this feat ure is to increase the effectiveness of board-level atpg patterns to isolate interconnect failures. 7.1 short pin descriptions n = port number (1 to 12 for ds32512, 1 to 8 for ds32508, 1 to 6 for ds32506). i = input, ipu = input with internal pullup resi stor, ipd = input with internal pulldown resistor, ia = analog input, i/o = bidirectional in/out, i/opd = bidirectional in/out with internal pulldown resistor, o = output, oz = high-impedance output (needs an external pullup or pulldown re sistor to keep the node from floating), oa = analog output ( high impedance), p = power supply or ground. all unused input pins without pullup should be tied low. note: all internal pullup resi stors are 50k tied to approximately 2.2v dc. see section 12 for pin assignments. table 7-1. short pin descriptions name type function analog line interface txpn oa transmit positive analog (port n) txnn oa transmit negative analog (port n) rxpn ia receive positive analog (port n) rxnn ia receive negative analog (port n) digital framer interface tclkn i transmit clock (port n) tposn / tdatn i transmit positive ami/transmit nrz data (port n) tnegn i transmit negative ami (port n) rclkn oz receive clock (port n) rposn / rdatn oz receive positive ami/receive nrz data (port n) rnegn / rlcvn oz receive negative ami/receive line code violation (port n) global i/o ifsel[2:0] i microprocessor interface select hw ipd hardware interface enable test i factory test enable (active low) hiz i high-impedance test enable (active low) rst ipu reset (active low) resref oa reference resistor hardware interface lmn[1:0] ipd liu mode control (ds3, e3, or sts-1) (port n) aist ipd ais type control (all ports) taisn ipd transmit ais control (port n) tbin ipd transmit binary interface control (all ports) tcc ipd transmit common clock control (all ports) tclki ipd transmit clock invert control (all ports) tdmn o transmit driver monitor status (port n) tlbon ipd transmit line build-out control (port n) toen ipd transmit output-ena ble control (port n) tpd ipd transmit power-down (all ports) itre i internal termination resistance enable (tx and rx) (all ports) rbin ipd receive binary interf ace control (all ports) rclki ipd receive clock invert control (all ports) rlosn o receive loss-of-signal status (port n) rmonn ipd receive monitor preamp control (port n) downloaded from: http:///
ds32506/ds32508/ds32512 15 of 130 name type function rpd ipd receive power-down (all ports) jad[1:0] ipd jitter attenuator depth (all ports) jas[1:0] ipd jitter attenuator select (tx, rx, or disabled) (port n) lbn[1:0] i loopback control (port n) lbs ipd loopback select (all ports) 8-/16-bit parallel interface cs i chip select (active low) rd / ds i read enable (active low) /data strobe (active low) wr / r/w i write enable (active low)/read/write select ale i address latch enable a[10:1] i address bus (excluding lsb) a[0] / bswap i address bus lsb/byte swap d[15:0] i/o data bus [15:0] rdy/ack oz ready/acknowledge (active low) int oz interrupt (active low) gpioan i/opd general-purpose i/o a (port n) gpiobn i/opd general-purpose i/o b (port n) spi serial interface cs i chip select (active low) sclk i serial clock sdi i serial data input sdo o serial data output cpha i clock phase cpol i clock polarity int oz interrupt output (active low) gpioan i/opd general-purpose i/o a (port n) gpiobn i/opd general-purpose i/o b (port n) clad refclk i reference clock clka i/o clock ads3 44.736mhz clkb i/o clock be3 34.368mhz clkc i/o clock csts-1 51.84mhz clkd o clock dtelecom bus 77.76mhz or 19.44mhz cladbyp i clad bypass jtag jtclk i jtag clock jtms i pu jtag mode select jtdi i pu jtag data input jtdo oz jtag data output jtrst i pu jtag reset (active low) power supply and ground pins vdd18 p digital core 1.8v power, 1.8v 5% vdd33 p i/o 3.3v power, 3.3v 5% vss p ground for vdd18 and vdd33 jvddn p jitter attenuator 1.8v power, 1.8v 5% (port n) jvssn p jitter attenuator ground (port n) rvddn p receive 1.8v power, 1.8v 5% (port n) downloaded from: http:///
ds32506/ds32508/ds32512 16 of 130 name type function rvssn p receive ground (port n) tvddn p transmit 1.8v power, 1.8v 5% (port n) tvssn p transmit ground (port n) cvdd p clad 1.8v 5% cvss p clad ground manufacturing test mt[10:0] test manufacturing test pins downloaded from: http:///
ds32506/ds32508/ds32512 17 of 130 7.2 detailed pin descriptions n = port number (1 to 12 for ds32512, 1 to 8 for ds32508, 1 to 6 for ds32506). i = input, ipu = input with internal pullup resi stor, ipd = input with internal pulldown resistor, ia = analog input, i/o = bidirectional in/out, i/opd = bidirectional in/out with internal pulldown resistor, o = output, oz = high-impedance output (needs an external pullup or pulldown resist or to keep the node from floating), oa = analog output (high impedance), p= power supply or ground. all unused input pins without pullup should be tied low. note: all internal pullup resistors are 50k tied to 2.2v dc. table 7-2. analog line in terface pin descriptions name type function txpn, txnn oa transmitter analog outputs. these differential ami outputs are coupled to the outbound 75 coaxial cable through a 1:1 transformer ( figure 4-1 ). these outputs can be disabled (high impedance) using the toen pin or the toe or tpd configuration bits. see section 8.2.8 . rxpn, rxnn ia receiver analog inputs. these differential ami inputs are coupled to the inbound 75 coaxial cable through a 1:1 transformer ( figure 4-1 ). see section 8.3.1 . table 7-3. digital framer interface pin descriptions name type function tclkn i transmit clock. a ds3 (44.736mhz 20ppm), e3 (34.368mhz 20ppm), or sts-1 (51.840mhz 20ppm) clock should be applied at this pin. data to be transmitted is clocked into the device at tpos / tdat and tneg either on the rising edge of tclk ( tclki = 0) or the falling edge of tclk ( tclki = 1). when pin tcc = 1, all ports are clocked by tclk1, and tclkx (x 1) are ignored. see section 8.2.1 for additional details. tposn/ tdatn i transmit positive ami/transmit nrz data. this pin is sampled either on the rising edge of tclk ( tclki = 0) or on the falling edge of tclk ( tclki = 1). see section 8.2.2 . tposn : when the transmitter is configured to have a bipolar interface ( tbin = 0), a positive pulse is transmitted on the line when tpos is high. tdatn : when the transmitter is configured to have a binary interface ( tbin = 1), the data on tdat is transmitted after b3zs or hdb3 encoding. tnegn i transmit negative ami. when the transmitter is configured to have a bipolar interface ( tbin = 0), a negative pulse is transmitted on the line when tneg is high. when the transmitter is configured to have a binary interface ( tbin = 1), tneg is ignored and should be wired either high or low. tneg is sampled either on the rising edge of tclk ( tclki = 0) or the falling edge of tclk ( tclki = 1). see section 8.2.2 . rclkn oz receive clock. the clock recovered from the receive signal is output on the rclk pin. recovered data is output on the rpos / rdat and rneg / rlcv pins on the falling edge of rclk ( rclki = 0) or the rising edge of rclk ( rclki = 1). during a loss-of-signal condition ( rlosn = 0), the rclk output signal is derived from the lius reference clock. see section 8.3.6 . rposn/ rdatn oz receive positive ami/receive nrz data. this pin is updated either on the falling edge of rclk ( rclki = 0) or the rising edge of rclk ( rclki = 1). see section 8.3.6 . rposn : when the receiver is configured to have a bipolar interface ( rbin = 0), rpos pulses high for each positive ami pulse received. rdatn : when the receiver is configured to have a binary interface ( rbin = 1), rdat outputs decoded binary data. rnegn/ rlcvn oz receive negative ami/receive line-code violation. this pin is updated either on the falling edge of rclk ( rclki = 0) or the rising edge of rclk ( rclki = 1). see section 8.3.6 for further details on code violations. rnegn : when the receiver is configured to have a bipolar interface ( rbin = 0), rneg pulses high for each negative ami pulse received. rlcvn: when the receiver is configured to have a binary interface ( rbin = 1), rlcv pulses high to flag code violations. downloaded from: http:///
ds32506/ds32508/ds32512 18 of 130 table 7-4. global pin descriptions name type function ifsel[2:0] i microprocessor interface select. when no microprocessor interface is selected, all microprocessor interface inputs are ignored and internally pulled low, and all microprocessor interface outputs are put in a high-impedance state. see section 6 for details. 000 = no microprocessor interface (must set hw = 1 and use hardware interface) 001 = reserved 010 = spi serial interface, address and data msb first 011 = spi serial interface, address and data lsb first 100 = 8-bit parallel interface, intel style ( cs , rd , wr control signals) 101 = 8-bit parallel interface, motorola style ( cs , r/w , ds control signals) 110 = 16-bit parallel interface, intel style ( cs , rd , wr control signals) 111 = 16- bit parallel interface, motorola style ( cs , r/w , ds control signals) hw ipd hardware interface enable. when the hardware interface pins are disabled, all hardware control inputs are ignored and internally pulled lo w, and all hardware status outputs are put in a high impedance state. see section 6 for details. 0 = hardware interface pins disabled 1 = hardware interface pins enabled test i factory test enable (active low). this pin enables the internal scan test mode when low. for normal operation tie high. this is an asynchronous input. hiz i high-impedance test enable (active low). this signal is used to enable testing. when this signal is low while jtrst is low, all the digital output and bidirectional pins are placed in the high-impedance state. for normal operation this signal is high. this is an asynchronous input. rst ipu reset (active low, open drain). when this global asynchronous reset is pulled low, all internal circuitry is reset and all internal registers are forced to their default values. the device is held in reset as long as rst is low. rst should be held low for at least two reference clock cycles. see section 8.11 . resref oa reference resistor. this pin is tied to vss through a 10k 1% resistor. this accurate resistor is used to calibrate on-chip resistor values including internal transmit and receive termination resistors. downloaded from: http:///
ds32506/ds32508/ds32512 19 of 130 table 7-5. hardware in terface pin descriptions name type function lmn[1:0] ipd liu mode control (port n). when only the hardware interface is enabled ( ifsel = 000 and hw = 1), these pins set the liu mode for port n. see section 8.1 . 00 = ds3 01 = e3 10 = sts-1 11 = reserved aist ipd ais type control (all ports). see section 8.2.3 . 0 = unframed all ones 1 = framed ds3 ais (ds3 mode), unframed al l ones (e3 mode), or ais-l (sts-1 mode) taisn ipd transmit ais control (port n). the type of ais signal is specified by the lmn[1:0] and aist pins. see section 8.2.3 . 0 = transmit normal data 1 = transmit ais tbin ipd transmit binary interface control (all ports). see section 8.2.2 . 0 = transmitter framer interface is bipolar on the tpos and tneg pins, and the b3zs/hdb3 encoder is disabled. 1 = transmitter framer interface is binary on the tdat pin, and the b3zs/hdb3 encoder is enabled. tcc ipd transmit common clock control (all ports). when this pin is high, the transmit paths of all ports are clocked by the tclk1 pin, and pins tclkx (x 1) are ignored. in designs where the transmit paths of all ports can be clocked synchronously with one another, this mode reduces wiring complexity between the liu and the neighboring framer or mapper component. see section 8.2.1 . tclki ipd transmit clock invert control (all ports). see section 8.2.1 . 0 = tpos / tdat and tneg are sampled on the rising edge of tclk . 1 = tpos / tdat and tneg are sampled on the falling edge of tclk . tdmn o transmit driver monitor status (port n). this pin reports the status of the transmit driver monitor. see section 8.2.9 for more information. 0 = transmit line driver is operating properly. 1 = transmit line driver is faulty. tlbon ipd transmit line build-out control (port n). this pin specifies cable length for waveform shaping in ds3 and sts-1 modes. in e3 mode it is ignored and should be wired high or low. see section 8.2.6 . 0 = cable length 225ft 1 = cable length < 225ft toen ipd transmitter output-enable control (port n). this pin enables and disables the transmitter outputs. the transmitter continues to operate internally when the outputs are disabled; only the line driver and driver monitor are disabled. see section 8.2.7 . 0 = txpn / txnn output drivers disabled (high impedance) 1 = txpn / txnn output drivers enabled tpd ipd transmit power-down (all ports). see section 8.2.10 . 0 = enable all transmitters 1 = power down all transmitters (drivers become high impedance) downloaded from: http:///
ds32506/ds32508/ds32512 20 of 130 name type function itre i internal termination resistance enable (tx and rx) (all ports). this bit indicates when the internal termination is enabled. see section 8.2.8 . 0 = disabled. the transmitters and receivers are terminated externally. 1 = enabled. the transmitters and receivers are terminated internally. rbin ipd receive binary interface control (all ports). see section 8.3.6 . 0 = receiver framer interface is bipolar on the rpos and rneg pins, and the b3zs/hdb3 encoder is disabled. 1 = receiver framer interface is binary on the rdat pin, and the b3zs/hdb3 encoder is enabled. rclki ipd receive clock invert control (all ports). see section 8.3.6.3 . 0 = rpos / rdat and rneg / rlcv update on the falling edge of rclk . 1 = rpos / rdat and rneg / rlcv update on the rising edge of rclk . rlosn o receive loss-of-signal status (port n). this pin is asserted upon detection of 192 consecutive zeros in the receive data stream. it is deasserted when there are no excessive zero occurrences over a span of 192 clock periods. an excessive zero occurrence is defined as three or more consecutive zeros in ds3 and sts-1 modes or four or more zeros in e3 mode. see section 8.3.5 . rmonn ipd receive monitor preamp control (port n). this pin determines whether or not the receiver preamp is enabled in port n to provide flat gain to the incoming signal before the agc/equalizer block processes it. this feature should be enabled when the device is being used to monitor signals that have been resistively attenuated by a monitor jack. see section 8.3.2 for more information. 0 = disable the monitor preamp 1 = enable the monitor preamp rpd ipd receive power-down (all ports). see section 8.3.7 . 0 = enable all receivers 1 = power down all receivers ( rxpn / rxnn high impedance. rclkn , rposn / rdatn , and rnegn / rlcvn high impedance.) jad[1:0] ipd jitter attenuator depth (all ports). these pins are ignored when a microprocessor interface is enabled ( ifsel 000). see section 8.4 . 00 = 16 bits 01 = 32 bits 10 = 64 bits 11 = 128 bits jas[1:0] ipd jitter attenuator select (all ports). these pins select the location of the jitter attenuator. these pins are ignored when a microprocessor interface is enabled ( ifsel 000). see section 8.4 . 00 = disabled 01 = receive path 1x = transmit path lbn[1:0] ipd loopback control (port n). when only the hardware interface is enabled ( ifsel = 000 and hw = 1), these pins set the loopback mode for port n. see section 8.6. 00 = no loopback 01 = diagnostic loopback (dlb) 10 = line loopback (llb) 11 = ( lbs = 0) line loopback (llb) and diagnostic loopback (dlb) simultaneously 11 = ( lbs = 1) analog loopback (alb) lbs ipd loopback select (all ports). this pin specifies how the device interprets the lbn[1:0] bits. this pin is ignored when a microprocessor interface is enabled ( ifsel 000). see section 8.6 . downloaded from: http:///
ds32506/ds32508/ds32512 21 of 130 table 7-6. parallel interface pin descriptions name type function cs i chip select (active low). this pin must be asserted to read or write internal registers. see section 8.8.3 . rd / ds i read enable (active low)/data strobe (active low) rd : for the intel-style bus ( ifsel = 1x0), rd is asserted to read internal registers. ds : for the motorola-style bus ( ifsel = 1x1), ds is asserted to access internal registers while the r/w pin specifies whether the access is a read or a write. see section 8.8.3 . wr /r/ w i write enable (active low)/read/write select wr : for the intel-style bus ( ifsel = 1x0), wr is asserted to write internal registers. r/w : for the motorola-style bus ( ifsel = 1x1), r/w determines the type of bus transaction, with r/w = 1 indicating a read and r/w = 0 indicating a write. see section 8.8.3 . ale i address latch enable. this pin controls a latch on the a [10:0] inputs. for a nonmultiplexed parallel bus, ale is wired high to make the latch transparent. for a multiplexed parallel bus, the falling edge of ale latches the address. see section 8.8.3 . a[10:1] i address bus (excluding lsb). these inputs specify the address of the internal 16-bit register to be accessed. a10 is not present on the ds32506. see section 8.8 . a[0] / bswap i address bus lsb/byte swap. see section 8.8.2 . a[0] : this pin is connected to the lower address bit in 8-bit bus modes ( ifsel = 10x). 0 = output register bits 7:0 on d[7:0]; d[15:8] high impedance 1 = output register bits 15:8 on d[7:0]; d[15:8] high impedance bswap : this pin is tied high or low in 16-bit bus modes ( ifsel = 11x). 0 = output register bits 15:8 on d[15:8] and bits 7:0 on d[7:0] 1 = output register bits 7:0 on d[15:8] and bits 15:8 on d[7:0] d[15:0] i/o data bus. a 8-bit or 16-bit bidirectional data bus. these pins are inputs during writes to internal registers and outputs during reads. d[15:8] are disabled (high impedance) in 8-bit bus modes ( ifsel = 10x). d[15:0] are disabled (high impedance) when cs = 1 or rst = 0. in 16-bit bus modes ( ifsel = 11x) the upper and lower bytes can be swapped by pulling the bswap pin high. see section 8.8 . rdy/ ack oz ready handshake (tri-state)/acknowledge handshake (tri-state, active low). tri-stated when cs = 1 or rst = 0. see section 8.8 . rdy: intel mode (ifsel = 100 or 110): rdy goes high when the read or write cycle can progress. ack : motorola mode (ifsel = 101 or 111): ack goes low when the read or write cycle can progress. int oz interrupt output (active low, open drain, or push-pull). this pin is driven low in response to one or more unmasked, active interrupt sources within the device. int remains low until the interrupt is serviced or masked. when global.cr2 :intm = 0, int is high impedance when inactive (default). when intm = 1, int is driven high when inactive. int is high impedance when rst = 0. see section 8.10 . gpioan i/opd general-purpose i/o a. when a microprocessor interface is enabled ( ifsel 000), this pin is the a general-purpose i/o pin for port n. see section 8.7.3 . gpiobn i/opd general-purpose i/o b. when a microprocessor interface is enabled ( ifsel 000), this pin is the b general-purpose i/o pin for port n. see section 8.7.3 . note: gpiob1, gpiob2, and gpiob3 can also be programmed as global control/status pins. downloaded from: http:///
ds32506/ds32508/ds32512 22 of 130 table 7-7. spi serial interface pin descriptions name type function cs i chip select (active low). this pin must be asserted to read or write internal registers. see section 8.9 . sclk i serial clock. sclk is always driven by the spi bus master. see section 8.9 . sdi i serial data input. the spi bus master transmits data to the device on this pin. see section 8.9 . sdo o serial data output. the device transmits data to the spi bus master on this pin. see section 8.9 . cpha i clock phase. see section 8.9 . 0 = data is latched on the leading edge of the sclk pulse 1 = data is latched on the trailing edge of the sclk pulse cpol i clock polarity. see section 8.9 . 0 = sclk is normally low and pulses high during bus transactions 1 = sclk is normally high and pulses low during bus transactions int oz interrupt output (active low, open drain). see int pin description in table 7-6 . gpioan i/opd general-purpose i/o a. see gpioan pin description in table 7-6 . gpiobn i/opd general-purpose i/o b. see gpiobn pin description in table 7-6 . table 7-8. clad pin descriptions name type function refclk i reference clock. the signal on this pin is the input reference clock to the clad and must be transmission quality ( 20ppm, low jitter). in hardware mode, refclk must be 19.44mhz. in bus interface modes, refclk can be any of several frequencies. see section 8.7.1 . clka i/o clock ads3 44.736mhz. when the clad is bypassed, a transmission-quality ds3 clock (44.736mhz 20ppm, low jitter) must be connected to this pin if any of the lius are to operate in ds3 mode. when the clad is ena bled this pin can be configured to output the ds3 clock synthesized by pll-a. see section 8.7.1 . clkb i/o clock be3 34.368mhz. when the clad is bypassed, a transmission-quality e3 clock (34.368mhz 20ppm, low jitter) must be connected to this pin if any of the lius are to operate in e3 mode. when the clad is enabled, this pin can be configured to output the e3 clock synthesized by pll-b. see section 8.7.1 . clkc i/o clock csts-1 51.84mhz. when the clad is bypassed, a transmission-quality sts-1 clock (51.84mhz 20ppm, low jitter) must be connected to this pin if any of the lius are to operate in sts-1 mode. when the clad is enabled, this pin can be configured to output the sts-1 clock synthes ized by pll-c. see section 8.7.1 . clkd o clock dtelecom bus 77.76mhz or 19.44mhz. when the clad is bypassed, this pin is driven low. when the clad is enabled this pin can output a 77.76mhz or 19.44mhz clock synthesized by pll-d. see section 8.7.1 . cladbyp i clad bypass control. this pin controls whether the cl ad is used or bypassed. when a microprocessor interface is enabled ( ifsel 000), cladbyp should be wired low to allow use of the global.cr2 :clad[6:0] field to control the clad. see section 8.7.1 . 0 = synthesize the ds3, e3, and sts-1 clocks from the clock on the refclk pin. 1 = source the ds3, e3, and sts-1 clocks from the clka , clkb and clkc pins. downloaded from: http:///
ds32506/ds32508/ds32512 23 of 130 table 7-9. jtag pin descriptions name type function jtclk i jtag clock. this pin shifts data into jtdi on the rising edge and out of jtdo on the falling edge. jtclk is typically a low frequen cy (less than 10mhz) 50% duty cycle clock signal. if boundary scan is not used, jtclk should be pulled high. see section 10 . jtms ipu jtag mode select. this pin is used to control the jtag controller state machine. jtms is sampled on the rising edge of jtclk. if boundary scan is not used, jtms should be left unconnected or pulled high. see section 10 . jtdi ipu jtag data input. this pin is used to input data into the register that is enabled by the jtag controller state machine. jtdi is samp led on the rising edge of jtclk. if boundary scan is not used, jtdi should be left unconnected or pulled high. see section 10 . jtdo oz jtag data output. this pin is the output of an internal scan shift register enabled by the jtag controller state machine. jtdo is updated on the falling edge of jtclk. jtdo is in high-impedance mode when a register is not selected or when the jtrst pin is low. jtdo goes into and out of high-impedance mode after the falling edge of jtclk. see section 10 . jtrst ipu jtag reset (active low). when active, this pin forces the jtag controller logic into the reset state and forces the jtdo pin into high-impedance mode. the jtag controller is also reset when power is first applied via a power-on reset circuit. jtrst can be driven high or low for normal operation, but must be high for jtag operation. see section 10 . table 7-10. power-supply pin descriptions name type function vdd18 p digital core 1.8v power, 1.8v 5% vdd33 p i/o 3.3v power, 3.3v 5% vss p ground for vdd18 and vdd33 jvddn p jitter attenuator 1.8v power, 1.8v 5% jvssn p jitter attenuator ground rvddn p receive 1.8v power, 1.8v 5% rvssn p receive ground tvddn p transmit 1.8v power, 1.8v 5% tvssn p transmit ground cvdd p clad 1.8v 5% cvss p clad ground table 7-11. manufacturing test pin descriptions name type function mt[10:0] test manufacturing test pins 10 to 0. mt[0] and mt[2:10] must not be connected. mt[1] must be connected to digital ground (same as vss pins). downloaded from: http:///
ds32506/ds32508/ds32512 24 of 130 8. functional description 8.1 liu mode each port is independently configur able for ds3, e3 or sts-1 operation. when only the hardware interface is enabled ( ifsel = 000 and hw = 1), the lmn[1:0] pins specify the liu mode. when a microprocessor interface is enabled ( ifsel 000) the port.cr2 :lm[1:0] control bits specify the liu mode. 8.2 transmitter 8.2.1 transmit clock if the jitter attenuator is not enabled in the transmit path, the signal on tclk is the transmit line clock and must be transmission quality (i.e., 20ppm frequency accuracy and low jitter). if the jitter attenuator is enabled in the transmit path, the signal on tclk can be jittery and/or periodically g apped, but must still have an average frequency within 20ppm of the nominal line rate. when enabled in t he transmit path, the ji tter attenuator generates the transmit line clock. see section 8.4 for more information about the jitter attenuator. the polarity of tclk can be inverted to support glueless interfacing to a variety of neighboring components. normally data is sampled on the tpos/ tdat and tneg pins on the rising edge of tclk . to sample these pins on the falling edge of tclk , pull the tclki pin high or set the port.inv :tclki configuration bit. 8.2.1.1 transmit common clock mode when the tcc pin is high, the transmit paths of all ports are clocked from tclk1 and pins tclkx (x 1) are ignored. when the tcc pin is low, the port.cr2 :tcc register bit specifies whether the transmit clock for port n comes from tclkn or tclk1. in designs where the transmit paths of all ports can be clocked synchronously with one another, common transmit clocking reduces wiring comp lexity between the liu and the neighboring framer or mapper component. 8.2.2 framer interface format and the b3zs/hdb3 encoder data to be transmitted can be input in either bipolar or binary format. 8.2.2.1 bipolar interface format to select the bipolar interface format, pull the tbin pin low and clear the port.cr2 :tbin configuration bit. in bipolar format, the b3zs/hdb3 encoder is disabled and the data to be transmitted is sampled on the tpos and tneg pins. positive-polarity pulses are indicated by tpos = 1, while negative-polarity pulses are indicated by tneg = 1. if tpos and tneg are high at the same time the transmitter generates an ami pulse that is the opposite state of the pulse previously transmitted. 8.2.2.2 binary interface format to select the binary interface format, pull the tbin pin high (all ports) or set the port.cr2 :tbin configuration bit (per port). in binary format, the b3zs/hbd3 encoder is enabl ed, and the nrz data to be transmitted is sampled on the tdat pin. the tneg pin is ignored in binary interface mode and should be wired low. in ds3 and sts-1 modes, b3zs encoding is performed. in these modes, w henever three consecutive zeros are found in the transmit data stream they are replaced with a b3zs codeword. in e3 mode hdb3 encoding is performed. in this mode, whenever four consecutive zeros are found in the transmit data stream they are replac ed with an hdb3 codeword. in all three modes, the b3zs or hdb3 codeword is constr ucted such that the last bit is a bpv with the opposite polarity of the most recently transmitted bpv. 8.2.3 error insertion bipolar violation (bpv) errors and excessive zeros (exz) errors can be in serted into the transmit data stream using the transmit manual error insert (tmei) logic (see section 8.7.5 ). configuration bit line.tcr :bpvi enables the insertion of bipolar violations, while line.tcr :exzi enables the insertion of ex cessive zero events. note: bpv errors and exz errors can only be inserted in the binary interface format. if the transmitter is configured for binary interface format (section 8.2.2.2 ) and bpvi = 1 then when the configured manual error insert control goes from zero to one, the tr ansmitter waits for the next occurrence of two consecutive downloaded from: http:///
ds32506/ds32508/ds32512 25 of 130 1s where the polarity of the first 1 is opposite the polarity of the bpv in the last b3zs/hdb3 codeword. the first 1 is transmitted according to the normal ami rule, but the second 1 is transmitted with the same polarity as the first 1, thus making the second 1 a bipolar violation. if the transmitter is configured for binary interface format (section 8.2.2.2 ) and exzi = 1, then when the configured manual error insert control goes from zero to one, the tr ansmitter waits for the next occurrence of three (four) consecutive zeros in the transmit data stream and inhibits the replacement of those zeros with a b3zs (hdb3) codeword. the transmitter ensure s that there is at least one intervening 1 between consecutive bpv or exz errors. if a second error insertion request of a given type (bpv or exz) is initiated before a previous request has been completed, the second request is ignored. 8.2.4 ais generation the transmitter can be configured to tr ansmit an ais signal by asserting the tais pin or the port.cr3 :tais configuration bit. the type of ais signal to be generated is specified by the liu mode ( lmn[1:0] pins or port.cr2 :lm[1:0] configuration bits) and the ais type ( aist pin or port.cr3 :aist configuration bit). when aist = 0, the ais signal is unframed all ones for ds3, e3 and sts-1 modes. when aist = 1, the ais signal is the framed ds3 ais signal in ds3 mode, unframed all ones in e3 mode, and the ais-l signal in sts-1 mode. the ais-l signal is normally scrambled, but scrambling can be disabled by setting port.cr3 :scrd = 1. 8.2.5 waveshaping 8.2.5.1 standards-compliant waveshaping waveshaping converts the transmit clock, positive data, and negative data signals into a single analog ami signal with the waveshape required for interfacing to ds3/e3/sts-1 lines. figure 8-1 and table 8-2 show the ds3 waveform equations and template. figure 8-2 and table 8-4 show the sts-1 waveform equations and template. figure 8-3 shows the e3 waveform template. 8.2.5.2 programmable waveshaping the transmit waveshape can be adjusted with the twsc[19:0] bits in the liu.twscr1 and liu.twscr2 registers. these signals control the am plitude, slew rates and various other as pects of the waveform template. see the register descriptions for further details. 8.2.6 line build-out because ds3 and sts-1 signals must meet the waveform te mplates at the cross-connect through any cable length from 0 to 450 feet, the waveshaping circuitry includes a se lectable lbo feature. for c able lengths of 225 feet or greater, both the tlbo pin and the liu.cr1 :tlbo configuration bit should be low to disable the lbo circuitry. when the lbo circuitry is disabled, output pulses are driven onto the coaxial cable wit hout any preattenuation. for cable lengths less than 225 feet, either the tlbo pin or the liu.cr1 :tlbo configuration bit should be high to enable the lbo circuitry. when the lbo circuitry is enabl ed, pulses are preattenuated by the lbo circuitry before being driven onto the coaxial cable to pr ovide attenuation that mimics the attenua tion of 225 feet of coaxial cable. 8.2.7 line driver the transmit line driver can be disabled ( txp and txn outputs high impedance) by deasserting the toe pin and deasserting the liu.cr1 :toe configuration bit. powering down the transmitter through the tpd pin or the port.cr1 :tpd configuration bit also disables the transmit line driver. 8.2.8 interfacing to the line the transmitter interfaces to the out going ds3/e3/sts-1 coaxial cable (75 ) through a 1:1 isolation transformer connected to the txp and txn pins. the transmit line termination can be internal to the device, external to the device, or a combination of both. figure 4-1 shows the arrangement of the transformer when the internal termination is enabled ( liu.cr1 :ttre = 1) and no external termination resistors are used. figure 4-2 shows the arrangement of the transformer and external terminati on resistors when the inter nal termination is disabled ( liu.cr1 :ttre = 0). the internal termination resistor value for the transmitter is specified in liu.cr1 :tresadj. table 8-7 and table 8-8 specify the required characteristics of t he transformer and provide a list of recommended transformers. downloaded from: http:///
ds32506/ds32508/ds32512 26 of 130 8.2.9 driver monitor and output failure detection the transmit driver monitor compares the amplit ude of the transmit waveform to thresholds v txmin and v txmax . if the amplitude is less than v txmin or greater than v txmax for approximately 32 mclk cycles, then the monitor activates the tdm output pin (if the hardware interface is enabled) and sets the liu.sr :tdm status bit. the setting of liu.sr :tdm can cause an interrupt if enabled by liu.srie :tdmie. when the transmitter is disabled, the transmit driver monitor is also disabled. the transmit dr iver monitor is clocked by the lius reference clock. note that the transmit driver monitor can be affected by re flections caused by shorts and opens on the line. a short circuit at a distance less than a few inches (~11 inches for fr-4 material) can introduce inverted reflections that reduce the outgoing pulse amplitude below the v txmin threshold and thereby activate the tdm pin and/or the tdm status bit. similarly an open circuit a similar distance aw ay can introduce noninverted re flections that increase the outgoing amplitude above the v txmax threshold and thereby activate the tdm pin and/or the tdm status bit. shorts and opens at larger distances away from txp / txn can also activate the tdm pin and/or the tdm status bit, but this effect is data-pattern dependent. if either txp or txn is not connected (open), shorted to v dd , or shorted to v ss , then a transmit failure alarm is declared by setting the liu.sr :tfail status bit. a change of state of the tfa il status bit can cause an interrupt if enabled by liu.srie :tfailie. tfail is cleared when activity is detected on both txp and txn . 8.2.10 power-down to minimize power consumption when the transmitter is not being used, the tpd pin (all ports) or the port.cr1 :tpd configuration bit (per port) can be assert ed. when the transmitter is powered down, the txp and txn pins are put in a high-impedance state and the transmit drivers are powered down. 8.2.11 jitter generation (intrinsic) the transmitter meets the jitter generation requirements of all applicable standards in table 8-1 , with or without the jitter attenuator enabled. generated jitter is measured with a jitter-free, 0ppm input clock. table 8-1. jitter generation ds325xx jitter without clad with clad signal standard requirement bandwidth typ max typ max units ds3 gr-499 0.3 ui rms 10hz to 400khz 0.01 0.02 0.01 0.02 ui rms ds3 t1.404 0.5 ui p-p 10hz to 400khz 0.02 0.03 0.05 0.06 ui p-p ds3 t1.404 0.05 ui p-p 30khz to 400khz 0.015 0.025 0.04 0.05 ui p-p e3 g.751 0.05 ui p-p 100hz to 800khz 0.02 0.03 0.04 0.05 ui p-p sts-1 gr-253 0.01 ui rms 12khz to 400khz 0.005 0.008 0.007 0.01 ui rms sts-1 gr-253 0.10 ui p-p 12khz to 400khz 0.04 0.06 0.06 0.08 ui p-p 8.2.12 jitter transfer without the jitter attenuator on the transmit side, the tr ansmitter passes jitter through unchanged. with the jitter attenuator enabled on the transmit side, the transmitter m eets the jitter transfer requirements of all applicable telecommunication standards in table 1-1 . see figure 8-7 . downloaded from: http:///
ds32506/ds32508/ds32512 27 of 130 figure 8-1. ds3 waveform template -0.5 -0.2 time (ui) 00 . 51 . 01 . 5 -1.0 0.8 1.0 1.2 0 0.2 normalized amplitude 0.4 0.6 -0.75 -0.25 0.25 0.75 1.25 2nd rise 1st rise 1st fall 2nd fall table 8-2. ds3 waveform equations time (in unit intervals) normalized amplitude equation upper curve -0.85 t -0.68 0.03 -0.68 t +0.36 0.5 {1 + sin[( / 2)(1 + t / 0.34)]} + 0.03 0.36 t 1.4 0.08 + 0.407e -1.84(t - 0.36) lower curve -0.85 t -0.36 -0.03 -0.36 t +0.36 0.5 {1 + sin[( / 2)(1 + t / 0.18)]} - 0.03 0.36 t 1.4 -0.03 table 8-3. ds3 waveform test parameters and limits parameter specification rate 44.736mbps ( 20ppm) line code b3zs transmission medium coaxial cable (at&t 734a or equivalent) test measurement point at the end of 0 to 450ft of coaxial cable test termination 75 ( 1%) resistive pulse amplitude between 0.36v and 0.85v pulse shape an isolated pulse (preceded by two zeros and followed by one zero) falls within the curves listed in table 8-2 . unframed all-ones power level at 22.368mhz between -1.8dbm and +5.7dbm unframed all-ones power level at 44.736mhz at least 20db less than the power at 22.368mhz pulse imbalance of isolated pulses ratio of positive and negative pulses must be between 0.90 and 1.10 ds325xx waveshape segments. see the liu.twscr register descriptions. downloaded from: http:///
ds32506/ds32508/ds32512 28 of 130 figure 8-2. sts-1 waveform template -0.5 normalized amplitude time (ui) 0 0.5 1.0 1.5 -0.75 -0.25 0.25 0.75 1.25 -0.2 0 0.2 -1.0 0.4 0.6 0.8 1.0 1.2 2nd rise 1st rise 1st fall 2nd fall table 8-4. sts-1 waveform equations time (in unit intervals) normalized amplitude equations upper curve -0.85 t -0.68 0.03 -0.68 t +0.26 0.5 {1 + sin[( / 2)(1 + t / 0.34)]} + 0.03 0.26 t 1.4 0.1 + 0.61e -2.4(t - 0.26) lower curve -0.85 t -0.36 -0.03 -0.36 t +0.36 0.5 {1 + sin[( / 2)(1 + t / 0.18)]} - 0.03 0.36 t 1.4 -0.03 table 8-5. sts-1 waveform t est parameters and limits parameter specification rate 51.840mbps ( 20ppm) line code b3zs transmission medium coaxial cable (at&t 734a or equivalent) test measurement point at the end of 0 to 450ft of coaxial cable test termination 75 ( 1%) resistive pulse amplitude 0.800v nominal (not covered in specs) pulse shape an isolated pulse (preceded by two zeros and followed by one zero) falls within the curved listed in table 8-4 . unframed all-ones power level at 25.92mhz between -1.8dbm and +5.7dbm unframed all-ones power level at 51.84mhz at least 20db less than the power at 25.92mhz ds325xx waveshape segments. see the liu.twscr register descriptions. downloaded from: http:///
ds32506/ds32508/ds32512 29 of 130 figure 8-3. e3 waveform template -5 -0.2 time (ns) 0 5 10 15 -15 0.8 1.0 1.2 0 0.2 normalized amplitude 0.4 0.6 -10 -0.1 0.1 0.5 0.9 1.1 29.1 (14.55 + 14.55) 24.5 (14.55 + 9.95) 14.55 12.1 (14.55 - 2.45) 8.65 (14.55 - 5.90) 17.0 (14.55 + 2.45) nominal pulse one level zero level overshoot undershoot zero level table 8-6. e3 waveform test parameters and limits parameter specification rate 34.368mbps ( 20ppm) line code hdb3 transmission medium coaxial cable (at&t 734a or equivalent) test measurement point at the transmitter test termination 75 ( 1%) resistive pulse amplitude 1.0v (nominal) pulse shape an isolated pulse (preceded by two zeros and followed by one or more zeros) falls within the template shown in figure 8-3 . ratio of the amplitudes of positive and negative pulses at the center of the pulse interval 0.95 to 1.05 ratio of the widths of positive and negative pulses at the nominal half amplitude 0.95 to 1.05 ds325xx waveshape segments. see the liu.twscr register descriptions. downloaded from: http:///
ds32506/ds32508/ds32512 30 of 130 8.3 receiver 8.3.1 interfacing to the line the receiver can be transformer-coupled or capacitor-coupl ed to the line. typically, the receiver interfaces to the incoming coaxial cable (75 ) through a 1:1 isolation transformer. the rece ive line termination can be internal to the device, external to the device, or a combination of both. figure 4-1 shows the arrangement of the transformer when the internal termination is enabled ( liu.cr2 :rtre = 1) and no external termination resistors are used. figure 4-2 shows the arrangement of the transformer and external termination resistors when the internal termination is disabled ( liu.cr2 :rtre = 0). the internal termination resistor value is specified in liu.cr2 :rresadj[3:0]. table 8-7 and table 8-8 specify the required characteristics of the transformer and provide a list of recommended transformers. the receiver expects the incoming si gnal to be in b3zs- or hdb3-coded ami format. table 8-7. transfo rmer characteristics parameter value turns ratio 1:1 2% bandwidth 75 0.200mhz to 340mhz (typ) primary inductance 40 h (min) leakage inductance 0.12 h (max) interwinding capacitance 10pf (max) isolation voltage 1500v rms (min) table 8-8. recommended transformers manufacturer part temp range pin- package/ schematic ocl primary ( h) (min) l l ( h) (max) bandwidth 75 (mhz) pulse engineering pe-65967 0c to +70c 6 smt ls-1/e 40 0.10 1500 pulse engineering pe-65966 0c to +70c 6 tht lc-1/e 40 0.10 1500 pulse engineering t3001 -40c to +85c 6 smt ls-2/e 40 0.11 1500 pulse engineering tx3025 -40c to +85c 16 smt bh/3 100 0.120 1500 pulse engineering tx3036 -40 c to +85c 24 smt 100 0.110 1500 pulse engineering tx3047 -40c to +85c 32 smt yb/1 100 0.150 1500 pulse engineering tx3051 -40c to +85c 48 smt 60 0.120 1500 halo electronics tg01-0406ns 0c to +70c 6 smt smd/a 40 0.10 1500 halo electronics td01-0406ns 0c to +70c 6 dip dip/a 40 0.10 1500 halo electronics tg01-0456ns -40c to +85c 6 smt smd/a 45 0.12 1500 halo electronics td01-0456ne -40c to +85c 6 dip dip/a 45 0.12 1500 note: table subject to change. multiport transformers are also available. contact the manufacturers for details at www.pulseeng.com and www.haloelectronics.com. 8.3.2 optional preamp the receiver can be used in monitoring applications that typically have series resistor s with a resistive loss of approximately 20db. when the rmon pin is high or the liu.cr2 :rmon configuration bit is set, the receiver can compensate for this resistive loss by applying 14db of additional flat gain to the incoming signal before sending the signal to the agc/equalizer block (an additional 6db of flat gain is applied in the agc circuitry for a total gain of 20db). when the preamp is enabled the receiver automatica lly determines whether or not to make use of the preamps additional gain. status bit liu.sr :rpas indicates whether or not the pr eamp is in use. a change of state of liu.sr :rpas can cause an interrupt if enabled by liu.srie :rpasie. 8.3.3 automatic gain control (agc) and adaptive equalizer the agc circuitry applies flat (frequency independent) gain to the incoming signal to compensate for flat losses in the transmission channel and variations in transmission power. since the incoming signal also experiences frequency-dependent losses as it passes through the co axial cable, the adaptive equalizer circuitry applies frequency-dependent gain to offset line losses and restore the signal. the agc/equalizer circuitry automatically adapts to coaxial cable losses from 0 to 22db, which transl ates into 0 to 457 meters (1500 feet) of coaxial cable downloaded from: http:///
ds32506/ds32508/ds32512 31 of 130 (at&t 734a or equivalent). the agc and the equalizer work simultaneously but independently to supply a signal of nominal amplitude and pulse shape to the clock and data recovery block. the agc/equ alizer block automatically handles direct (0 meters) monitoring of the transmitter out put signal. the real-time receiver gain level can be read from the liu.rglr register. note: when the receiver preamp is on ( liu.sr :rpas = 1), the actual receiver gain level is the level read from the liu.rglr register plus 14db. 8.3.4 clock and data recovery (cdr) the cdr block takes the amplified, equalized signal from the agc/equalizer block and produces separate clock, positive data, and negative data signals. the cdr opera tes from the lius reference clock. see section 8.7.1 for more information about reference clocks and clock selection. the receiver locks onto the incoming signal using a clock re covery pll. the pll lock status is indicated in the liu.sr :rlol status bit. the rlol bit is set when the difference between recovered clock frequency and reference clock frequency is greater than 7900ppm and cleared when the difference is less than 7700ppm. a change of state of the rlol status bit can cause an interrupt if enabled by liu.srie :rlolie. note that if the reference clock is not present, rlol is not set. 8.3.5 loss-of-signal (los) detector the receiver contains analog and digital los detectors. the analog los (alos) detector resides in the agc/equalizer block. at approximately 23db below nomi nal pulse amplitude alos is declared by setting the liu.sr :alos status bit. a change of state of the alos status bit can cause an interrupt if enabled by liu.srie :alosie. when alos is declared the cdr block forces all zeros out of the data recovery circuit, causing digital los (dlos), which is indicated by the rlos pin and the line.rsr :los status bit. during alos the rclk pin follows the lius reference clock, since no clock information is being received on rxp / rxn . alos is cleared at approximately 22db below nominal pulse amplit ude. when the preamp is enabled (section 8.3.2 ) alos is declared at approximately 37db below nominal and cleared at approximately 36db below nominal. the digital los detector declares dlos when it detects 192 consecutive zeros in the recovered data stream. when dlos occurs, the receiver asserts the rlos pin (if the hardware interface is enabled) and the line.rsr :los status bit. dlos is cleared when there are no exz occurrences over a span of 192 clock periods. an exz occurrence is defined as three or more consecutive zeros in ds3 and sts-1 modes and four or more consecutive zeros in e3 mode. the rlos pin and the los status bit are deasserted when the dlos condition is cleared. a change of state of the line.rsr :los status bit can cause an interrupt if enabled by line.rsrie :losie. dlos is only declared when b3zs/hdb3 decoding is enabled ( line.rcr :rzsd = 0). when b3zs/hdb3 decoding is disabled in the liu, decoding should be enabled in the neighboring ds3/e3 framer, and dlos should be detected and report by the framer. the requirements of ansi t1.231 and itu-t g.775 for ds3 los defects are met by the dlos detector, which asserts rlos when it counts 192 consecutive zeros coming out of the cdr block and clears rlos when it counts 192 consecutive pulse intervals without excessive zero occurrences. the requirements of itu-t g.775 for e3 los defects ar e met by a combination of the alos detector and the dlos detector, as follows: for e3 rlos assertion: 1) the alos detector in the agc/equalizer block det ects that the incoming signal is less than or equal to a signal level approximately 23db below nominal, and mutes the data coming out of the clock and data recovery block. (23db below nominal is in the tolerance range of g.775, where los may or may not be declared.) 2) the dlos detector counts 1 92 consecutive zeros coming out of the cdr block and asserts rlos. (192 meets the 10 n 255 pulse-interval duration requirement of g.775.) for e3 rlos clear: 1) the alos detector in the agc/equalizer block de tects that the incoming signal is greater than or equal to a signal level approximately 22db below nominal, and enables data to come out of the cdr block. (22db is in the tolerance range of g.775, where los may or may not be declared.) 2) the dlos detector counts 192 consecutive pulse intervals without exz occurrences and deasserts rlos. (192 meets the 10 n 255 pulse-interval duration requirement of g.775.) downloaded from: http:///
ds32506/ds32508/ds32512 32 of 130 the dlos detector supports the requirements of ansi t1 .231 for sts-1 los defects. at the sts-1 rate, the time required for the dlos detector to count 192 co nsecutive zeros falls in the range of 2.3 t 100 s required by ansi t1.231 for declaring an los defect. although the time required for the dlos detector to count 192 consecutive pulse intervals with no excessive zeros is less than the 125 s to 250 s period required by ansi t1.231 for clearing an los defect, a period of this length wh ere los is inactive can easily be timed in software. during los, the rclk output pin is derived from the lius reference clock. the alos detector has a longer time constant than the dlos detector. thus, when the incoming signal is lost, the dlos detector activates first (asserting the rlos pin and los status bit), followed by the alos detector. when a signal is restored, the dlos detector does not get a valid signal that it can qualify for no exz occurrences until the alos detector has seen the signal rise above a signal level approximately 22db below nominal. 8.3.6 framer interface format and the b3zs/hdb3 decoder the recovered data can be output in either bipolar or bi nary format. reception of a b3zs or hdb3 codeword is flagged by the line.rsrl :zscdl latched status bit. 8.3.6.1 bipolar interface format to select the bipolar interface format, pull the rbin pin low and clear the port.cr2 :rbin configuration bit. in bipolar format, the b3zs/hdb3 decoder is disabled and the recovered data is buffered and output on the rpos and rneg outputs for subsequent decoding by a downstream framer or mapper. received positive-polarity pulses are indicated by rpos = 1, while negative-polarity pulses are indicated by rneg = 1. in ds3 and sts-1 modes an excessive zeros error (exz) is declared whenever there is an occurrence of 3 or more zeros in a row in the receive data stream. in e3 mode, an exz error is declared whenever there is an occurrence of 4 or more zeros. exzs are flagged by the line.rsrl :exzl and exzcl latched status bits and accumulated in the line.rexzcr register. in all three modes (ds3, e3, and sts-1) a bipolar violation is declared if two positive pulses are received without an intervening negative pulse or if two negative pulses are received without an intervening positive pulse. bipolar violations (bpvs) are flagged by the line.rsrl :bpvl and bpvcl latched status bits and accumulated in the line.rbpvcr register. 8.3.6.2 binary interface format to select the binary interface format, pull the rbin pin high (all ports) or set the port.cr2 :rbin configuration bit (per port). in binary format, the b3zs/hbd3 decoder is enabled, and the recovered data is decoded and output as a binary (nrz) value on the rdat pin, while bipolar violations, code violations, and excessive zero errors are detected and flagged on the rlcv pin. in ds3 and sts-1 modes, b3zs decoding is performed. in these modes, whenever a b3zs codeword is found in the receive data stream it is replaced with three zeros. in e3 mode hdb3 decoding is performed. in this mode, whenever an hdb3 codeword is found in the receive data stream it is replaced with four zeros. the decoding search criteria for a b3zs/hdb3 codeword is programmable using the line.rcr :rdzsf control bit. an excessive zeros error (exz) is declared in ds3 and sts-1 modes whenever there is an occurrence of 3 or more zeros in a row in the receive data stream. in e3 mode, an exz error is declared whenever there is an occurrence of 4 or more zeros in a row. exzs are flagged by the line.rsrl :exzl and exzcl latched status bits and accumulated in the line.rexzcr register. a bipolar violation error (bpv error) is declared in ds3 and sts-1 modes if a bpv is detected that is not part of a valid b3zs codeword. in e3 mode, a bi polar violation error is declared whenever a bpv is detected that is not part of a valid hdb3 codeword. in e3 mode if line.rcr :e3cve = 1, code violations are detected rather than bipolar violation errors. a code viol ation is declared whenever co nsecutive bpvs (not bpv erro rs) have the same polarity (itu o.161 definition). the error detection search criter ia for a b3zs/hdb3 codeword is programmable using the line.rcr :rezsf control bit. bipolar violations (or code violations if line.rcr :e3cve = 1) are flagged by the line.rsrl :bpvl and bpvcl latched status bits and accumulated in the line.rbpvcr register. in the discussion that follows, a valid pulse that conforms to the ami rule is denoted as b. a bpv pulse that violates the ami rule is denoted as v. in ds3 and sts-1 modes, b3zs decoding is performed, and rlcv is asserted during any rclk cycle where the data rdat causes ones of the following code violations: downloaded from: http:///
ds32506/ds32508/ds32512 33 of 130 when 8 line.rcr :e3cve = 0: C a bpv immediately preceded by a valid pulse (b, v). C a bpv with the same polarity as the last bpv. C the third zero in an exz. when 8 line.rcr :e3cve = 1: C a bpv immediately preceded by a valid pulse (b, v). C a bpv with the same polarity as the last bpv. in e3 mode, hdb3 decoding is performed, and rlcv is asserted during any rclk cycle where the data on rdat causes one of the following code violations: when 18 line.rcr :e3cve = 0: C a bpv immediately preceded by a valid pulse (b, v) or by a valid pulse and a zero (b, 0, v). C a bpv with the same polarity as the last bpv. C the fourth zero in an exz. when 18 line.rcr :e3cve = 1: C a bpv with the same polarity as the last bpv. in any cycle where rlcv is asserted to flag a bpv, the rdat pin outputs a one. in any cycle where rlcv is asserted to flag an exz, the rdat pin outputs a zero. the state bit that tr acks the polarity of the last bpv is toggled on every bpv, whether part of a valid b3zs/hdb3 codeword or not. 8.3.6.3 rclk inversion the polarity of rclk can be inverted to support a glueless interface to a variety of neighboring components. normally, data is output on the rpos / rdat and rneg / rlcv pins on the falling edge of rclk . to output data on these pins on the rising edge of rclk , pull the rclki pin high or set the port.inv :rclki configuration bit. 8.3.6.4 receiver output disable the rclk , rpos / rdat and rneg / rlcv pins can be disabled (put in a high-impedance state) to support protection switching and redundant-liu applications. this capability supports system configurations where two or more lius are wire-ored together and a system processor selects one to be active. to disable these pins, set the port.cr2 :rod configuration bit. 8.3.7 power-down to minimize power consumption when the receiver is not being used, assert the rpd pin (all ports) or the port.cr1 :rpd configuration bit (per port). when the receiver is powered down, the rclk , rpos / rdat , and rneg / rlcv pins are disabled (high impedance). in addition, the rxp and rxn pins become high impedance. 8.3.8 input failure detection the liu receiver can detect opens and shorts on the rxp and rxn differential inputs. by default, the receiver detects the following problems, collectively labeled type 1 failures: open rxp connection, open rxn connection, common-mode rxp / rxn short to v dd , and common-mode rxp / rxn short to v ss . type 1 failures are reported on liu.sr :rfail1. rfail1 is cleared when activity is detected on both rxp and rxn . if liu.cr2 :rfl2e = 1, the receiver also detects a type 2 failu re, which is an open or high-impedance path between rxp and rxn . in a board with the external components shown in figure 4-1 or figure 4-2 , the receive transformer normally presents a low-impedance path between rxp and rxn . to detect a type 2 failure, the receiver connects an 40 a dc current source to rxp and measures the impedance between rxp and rxn . when this impedance is greater than about 5k the receiver declares a type 2 failure on liu.sr :rfail2. when the type 2 failure detection circuitry is enabled, internal termination must be disabled ( liu.cr2 :rtre = 0) and external termination must not be present or a type 2 failure will not be detected becaus e the impedance of the termination is below the type 2 failure threshold. downloaded from: http:///
ds32506/ds32508/ds32512 34 of 130 8.3.9 jitter and wander tolerance the receiver exceeds the input jitter tolerance require ments of all applicable telecommunication standards in table 1-1 . see figure 8-4 for sts-1 and e3 jitter tolerance characteristics. see figure 8-5 for ds3 jitter tolerance characteristics. see figure 8-6 for ds3 and e3 wander tolerance characteristics. note: only g.823 and g.824 have wander tolerance requirements. figure 8-4. sts-1 and e3 jitter tolerance 10 0.1 1.0 10 800k 300 30 g.823 (e3) ds325xx jitter tolerance gr-253 (sts-1) jitter tolerance (ui p-p ) frequency (hz) 100 1k 10k 100k 1m 15 1.5 0.15 2k 20k 1 100 4.4 34.4 1.675 figure 8-5. ds3 jitter tolerance 10 60k 600 0.1 1.0 10 300k ds325xx jitter tolerance jitter tolerance (ui p-p ) frequency (hz) 100 1k 10k 100k 1m gr-499 cat i (ds3) gr-499 cat ii (ds3) 5 2.3k 22.3k 0.3 1 100 g.824 (ds3) 400k 30k 669 21.9 67 1.675 downloaded from: http:///
ds32506/ds32508/ds32512 35 of 130 figure 8-6. ds3 and e3 wander tolerance 10 10 100 0.13 ds325xx wander tolerance wander tolerance (ui p-p ) frequency (hz) 1 1000 4.4 34.4 10 -1 10 -2 137.5 0.032 g.823 (e3) g.824 (ds3) 67 1.675 805 10 -3 10 -4 10 -5 1.2 6.12 8.3.10 jitter transfer without the jitter attenuator on the receive side, the rece iver attenuates jitter at frequencies above its corner frequency (approximately 300khz) and passes jitter at lower frequencies. with the jitter attenuator enabled on the receive side, the receiver meets the jitter transfer requi rements of all applicable telecommunication standards in table 1-1 . see figure 8-7 . 8.4 jitter attenuator each liu contains an on-board jitter attenuator that can be placed in the receive path or the transmit path or can be disabled. when only the hardware interface is enabled ( ifsel = 000 and hw = 1), the jas[1:0] and jad[1:0] pins specify the specify the ja location and buffer depth for all ports. when a microprocessor interface is enabled ( ifsel 000), the jas[1:0] and jad[1:0] pins are ignored, and the liu.cr1 :jas[1:0] and jad[1:0] configuration bits specify the ja location and buffer depth for each port individually. the ja buffer depth can be set to 16, 32, 64 or 128 bits. figure 8-7 shows the minimum jitter attenuation for the device when the jitter attenuator is enabled. figure 8-7 also shows the receive jitter transfer when the jitter attenuator is disabled. the jitter attenuator consists of a narrowband pll to reti me the selected clock, a fifo to buffer the associated data while the clock is being retimed, and logic to prevent fifo over/underflow in the presence of very large jitter amplitudes. the ja has a loop bandwidth of reference_clock 2,058,874 (see corner frequencies in figure 8-7 ). the ja attenuates jitter at frequencies higher than the loop bandwidth, while allowing jitter (and wander) at lower frequencies to pass through relatively unaffected. the jitter attenuator requires a transmission-quality reference clock (i.e., 20ppm frequency accuracy and low jitter). see section 8.7.1 for more information about reference clocks and clock selection. when the microprocessor interface is enabled, the jitter att enuator indicates the fill status of its fifo buffer in the liu.srl :jafl (ja full) and liu.srl :jael (ja empty) status bits. when the buffer becomes full, the ja momentarily increases the frequency of the read clock by 6250ppm to avoid buffer overflow and consequent data errors. when the buffer becomes empty, the ja moment arily decreases the frequency of the read clock by 6250ppm to avoid buffer underflow and consequent data errors. during these momentary frequency adjustments, jitter is passed through the ja to avoid over/underflow. if the phase noise or frequency offset of the write clock is large enough to cause the buffer to overflow or underflow, the ja sets both the jafl bit a n d the jael bit to indicate that data errors have occurred. jafl and j ael can cause an interrupt if enabled by the corresponding enable bits in the liu.srie register. as shown in figure 8-7 , the jitter attenuator meets the jitter transfer requirements of all applicable standards listed in table 1-1 . downloaded from: http:///
ds32506/ds32508/ds32512 36 of 130 figure 8-7. jitter attenua tion/jitter transfer 10 100 1k 10k 100k 1m 21.7 hz (ds3) 16.7 hz (e3) 25.2 hz (sts -1) 1k -30 -20 -10 e3 [tbr24 (1997)] frequency (hz) jitter a ttenuation (db) 0 ds3 [gr - 499 (1995)] category i ds325xx typical receiver jitter transfer with jitter attenuator disabled >150k ds325xx ds3/e3/sts -1 minimum jitter attenuation with jitter attenuator enabled 40hz ds3 [gr - 253 (1999)] category i 27hz sts- 1 [gr - 253 (1999)] category ii 40k 59.6k ds3 [gr - 499 (1999)] category ii 8.5 bert each liu port has a built-in bit error-rate tester ( bert). the bert is a software-programmable test-pattern generator and monitor capable of meeting most error performance requirements for digital transmission equipment. it can generate and synchronize to pseudo-random patte rns with a generation polynomial of the form x n + x y + 1, (where n and y can take on values from 1 to 32 with y < n) and to repetitive patterns of any length up to 32 bits. the pattern generator generates the programmable test pattern, and inserts the test pattern into the data stream. the pattern detector extracts the test pattern from the receive data stream and monitors it. figure 2-1 shows the location of the bert block within the ds325xx devices. 8.5.1 configuration and monitoring the pattern detector is always enabled. the pattern generator is enabled by setting the port.cr3 :berte configuration bit. when the bert is enabled and port.cr3 :bertd=0, the pattern is transmitted and received in the line direction, i.e. the pattern generator is the data source for the transmitter, and the receiver is the data source for the pattern detector. when the bert is enabled and port.cr3 :bertd=1, the pattern is transmitted and received in the system direction, i.e. the pattern generator is the data source for the rpos / rdat and rneg / rlcv pins, and the tpos / tdat and tneg pins are the data source for the pattern detector. see figure 2-1 . the i/o of the bert are binary (nrz) format. thus while the bert is enabled, both port.cr2 :rbin and port.cr2 :tbin must be set to 1 for proper operation. in addition, while transmitting/receiving bert patterns in the system direction ( port.cr3 :bertd = 1), the neighboring framer or mapper component must also be configured for binary interface mode to match the liu. if the liu interface is normally bipolar, the interface can be changed back to bipolar mode when the system is done using the bert function ( port.cr3 :berte = 0). the following tables show how to configure the bert to send and receive common patterns. downloaded from: http:///
ds32506/ds32508/ds32512 37 of 130 table 8-9. pseudorandom pattern generation bert.pcr register bert.cr pattern type ptf[4:0] (hex) plf[4:0] (hex) pts qrss bert.spr2 bert.spr1 tpic, rpic 2 9 -1 o.153 (511 type) 04 08 0 0 0xffff 0xffff 0 2 11 -1 o.152 and o.153 (2047 type) 08 0a 0 0 0xffff 0xffff 0 2 15 -1 o.151 0d 0e 0 0 0xffff 0xffff 1 2 20 -1 o.153 10 13 0 0 0xffff 0xffff 0 2 20 -1 o.151 qrss 02 13 0 1 0xffff 0xffff 0 2 23 -1 o.151 11 16 0 0 0xffff 0xffff 1 table 8-10. repetitive pattern generation bert.pcr register pattern type ptf[4:0] (hex) plf[4:0] (hex) pts qrss bert.spr2 bert.spr1 all 1s na 00 1 0 0xffff 0xffff all 0s na 00 1 0 0xffff 0xfffe alternating 1s and 0s na 01 1 0 0xffff 0xfffe 11001100... na 03 1 0 0xffff 0xfffc 3 in 24 na 17 1 0 0xff20 0x0022 1 in 16 na 0f 1 0 0xffff 0x0001 1 in 8 na 07 1 0 0xffff 0xff01 1 in 4 na 03 1 0 0xffff 0xfff1 after configuring these bits, the pattern must be loaded into the bert. this is accomplished via a zero-to-one transition on bert.cr .tnpl for the pattern generator and bert.cr .rnpl for the pattern detector. the bert must be enabled ( port.cr3 :berte = 1) before the pattern is loaded for the pattern load operation to take effect. monitoring the bert requires reading the bert.sr register, which contains the bit-error count (bec) bit and the out of synchronization (oos) bit. the bec bit is set to one when the bit error counter is one or more. the oos bit is set to one when the pattern detector is not synchronized to the incoming pattern, whic h occurs when it receives 6 or more bit errors within a 64-bit window. the receive bert bit count register ( bert.rbcr ) and the receive bert bit error-count register ( bert.rbecr ) are updated upon the reception of a performance monitor update signal (e.g., bert.cr .lpmu). this signal updates the registers with the bit and bit-error counts since the last update and then resets the counters. see section 8.7.4 for more details about performance monitor updates. 8.5.2 receive pattern detection the pattern detector synchronizes the receive pattern generator to the incoming pattern. the receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (lsb) or bit 1 to the most significant bit (msb) or bit 32. the input to bit 1 is the feedback. for a prbs pattern (generating polynomial x n + x y + 1), the feedback is an xor of bit n and bit y. for a repetitive pattern (length n), the feedback is bit n. the values for n and y are individually programmable (1 to 32 with y < n) in the bert.pcr :plf and ptf fields. the output of the receive pattern generator is the feedback. if qrss is enabled ( bert.pcr :qrss = 1), the feedback is forced to be an xor of bits 17 and 20, and the output is forced to one if the next 14 bits are all zeros. for prbs and qrss patterns, the feedback is forced to one if bits 1 thro ugh 31 are all zeros. depending on the type of pattern programmed, pattern detection performs either prbs synchronization or repetitive pattern synchronization. downloaded from: http:///
ds32506/ds32508/ds32512 38 of 130 8.5.2.1 receive prbs synchronization prbs synchronization synchronizes the receive pattern ge nerator to the incoming prbs or qrss pattern. the receive pattern generator is synchronized by loading 32 dat a stream bits into the receive pattern generator, and then checking the next 32 data stream bits. synchronization is achieved if all 32 bits match the incoming pattern. if at least six incoming bits in the current 64-bit window do not match the receive pattern generator, automatic pattern resynchronization is initiated. automatic pattern resynchronization can be disabled by setting bert.cr :aprd = 1. pattern resynchronization can also be initiated manually by a zero-to-one transition of the manual pattern resynchronization bit ( bert.cr :mpr). the incoming data stream can be inverted before comparison with the receive pattern generator by setting bert.cr :rpic. see figure 8-8 for the prbs synchronization diagram. figure 8-8. prbs synchr onization state diagram sync load verify 1 bit error 32 bits loaded 3 2 b it s w it h o u t er ro rs 6 o f 64 b i t s w i t h e r ro rs 8.5.2.2 receive repetitive pattern synchronization repetitive pattern synchronization synchronizes the rece ive pattern generator to the incoming repetitive pattern. the receive pattern generator is synchronized by searching each incoming data stream bit position for the repetitive pattern, and then checking the next 32 data stream bits. synchronization is achieved if all 32 bits match the incoming pattern. if at least six incoming bits in the current 64-bit window do not match the receive prbs pattern generator, automatic pattern resynchronization is initiated. automatic pattern re-synchronization can be disabled by setting bert.cr :aprd = 1. pattern resynchronization can also be initiated manually by a zero-to-one transition of the manual pattern resynchronization bit ( bert.cr :mpr). the incoming data stream can be inverted before comparison with the receive pattern generator by setting bert.cr :rpic. see figure 8-9 for the repetitive pattern sy nchronization state diagram. downloaded from: http:///
ds32506/ds32508/ds32512 39 of 130 figure 8-9. repetitive pattern synchronization state diagram sync match verify 1 bit error pattern matches 3 2 b it s w it h out er rors 6 of 6 4 b it s w it h er r or s 8.5.2.3 receive pattern monitoring receive pattern monitoring monitors the incoming data stream for both an oos condition and bit errors and counts the incoming bits. an out of synchronization ( bert.sr :oos = 1) condition is declared when the synchronization state machine is not in the sync st ate. an oos condition is terminated w hen the synchronization state machine is in the sync state. a change of state of the oos status bit sets the bert.srl :oosl latched status bit and can cause an interrupt if enabled by bert.srie :oosie. bit errors are determined by comparing the incoming data st ream bit to the receive pattern generator output. if the two bits do not match, a bit error is declared ( bert.srl :bel = 1), and the bit error and bit counts are incremented ( bert.rbecr and bert.rbcr , respectively). if the two bits do match, only the bit count is incremented. the bit count and bit error count are not incremented when an oos condition exists. the setting of the bel status bit can cause an interrupt if enabled by bert.srie :beie. 8.5.3 transmit pattern generation the pattern generator generates the outgoing test pattern. the transmit pattern generator is a 32-bit shift register that shifts data from the least significant bit (lsb) or bit 1 to the most significant bit (msb) or bit 32. the input to bit 1 is the feedback. for a prbs pattern (generating polynomial x n + x y + 1), the feedback is an xor of bit n and bit y. for a repetitive pattern (length n), the feedback is bit n. the values for n and y are individually programmable (1 to 32 with y < n) in the bert.pcr :plf and ptf fields. the output of the re ceive pattern generator is the feedback. if qrss is enabled ( bert.pcr :qrss = 1), the feedback is forced to be an xor of bits 17 and 20, and the output is forced to one if the next 14 bits are all zeros. for pr bs and qrss patterns, the feedback is forced to one if bits 1 through 31 are all zeros. when a new pattern is loaded, the pattern generator is loaded with a seed/pattern value before pattern generation starts. the seed/pattern value is programmable (0 - 2 n - 1) in the bert.spr registers. the generated pattern can be inverted by setting bert.cr :tpic. downloaded from: http:///
ds32506/ds32508/ds32512 40 of 130 8.5.3.1 transmit error insertion errors can be inserted into the generated pattern one at a time or at a rate of one out of every 10 n bits. the value of n is programmable (1 to 7 or off) in the bert.teicr :teir[2:0] configuration field. single bit error insertion is enabled by setting bert.teicr :bei and can be initiated from the microp rocessor interface or by the manual error insertion pin (gpiob2). see section 8.7.5 for more information about manual error insertion. 8.6 loopbacks each liu has three internal loopbacks. see figure 2-1 . when only the hardware interface is enabled ( ifsel = 000 and hw = 1), loopbacks are controlled by the lbn[1:0] and lbs pins. when a microprocessor interface is enabled ( ifsel 000), loopbacks are controlled by the lb[1:0] and lbs fields in the port.cr3 register. analog loopback (alb) connects the outgoing transmit signal back to the receivers analog front end. during alb the transmit signal is output normally on txp / txn , but the received signal on rxp / rxn is ignored. line loopback (llb) connects the output of the receiver to the input of the transmitter. the llb path does not include the b3zs/hdb3 decoder and encoder so that t he signal looped back is exactly the same as the signal received, including bipolar violations and code violati ons. during llb, recovered clock and data are output on rclk , rpos / rdat , and rneg / rlcv , but the tpos / tdat and tneg pins are ignored. diagnostic loopback (dlb) connects the tclk, tpos/tdat and tneg pins to the rclk , rpos / rdat, and rneg / rlcv pins. during dlb (with llb disabled), the signal on txp / txn can be the normal transmit signal or an ais signal from the ais generator. dlb and llb can be enabled simultaneously to provide simultaneous remote and local loopbacks. 8.7 global resources 8.7.1 clock rate adapter (clad) the clad is used to create multiple transmission-quality reference clocks from a single transmission-quality ( 20ppm, low jitter) clock input on the refclk pin. the lius in the device need up to three different reference clocks (ds3, e3, and sts-1) for use by the cdrs and jitte r attenuators. given one of these clock rates or any of several other clock frequencies on the refclk pin, the clad can generate all three liu reference clocks. the internally generated reference clock si gnals can optionally be driven out on pins clka , clkb , and clkc for external use. in addition a fourth frequency, either 77.76mhz or 19.44mhz, can be generated and driven out on the clkd pin for use in telecom bus applications. when only the hardware interface is enabled ( ifsel = 000 and hw = 1), the clad is controlled by the cladbyp pin, and the refclk frequency is fixed at 19.44mhz. when the cladbyp pin is high all plls in the clad are bypassed and powered down, and the refclk pin is ignored. in this mode the clka , clkb , and clkc pins become inputs, and the ds3, e3, and sts-1 reference clocks, respectively, are sourced from these pins. transmission-quality clocks ( 20ppm, low jitter) must be provided to these pins for each line rate required by the lius. when cladbyp is low, all four plls in the clad are enabled, and the generated ds3, e3, sts-1, and 77.76mhz clocks are always output on clka , clkb , clkc and clkd , respectively. when a microprocessor interface is enabled ( ifsel 000), the clad clock mode and the refclk frequency are set by the global.cr2 :clad[6:4] bits, as shown in table 8-11 . when clad[6:4] = 000, all plls in the clad are bypassed and powered down, and the refclk pin is ignored. in this mode the clka , clkb , and clkc pins become inputs, and the ds3, e3, and sts-1 reference clocks, respectively, are sourced from these pins. transmission-quality clocks ( 20ppm, low jitter) must be provided to these pins for each line rate required by the lius. clad[6:4] = 000 is equivalent to pulling the cladbyp pin high. when clad[6:4] 000, the pll circuits are enabled as needed to generate the required clocks, as determined by the clad[6:0] bits and the liu mode bits ( port.cr2 :lm[1:0]). if a clock rate is not required as a refe rence clock, then the pll used to generate that clock is automatically disabled and powered down. the clad[3:0] bits are output enable controls for clka , clkb , clkc and clkd , respectively. configuration bit global.cr2 :clkd19 specifies the frequency to be output on the clkd pin (77.76mhz or 19.44mhz). status register global.srl provides activity status for the refclk, clka , clkb and clkc pins and lock status for the clad. each liu block indicates the absence of the reference clock it requires by setting its liu.sr :lomc bit. downloaded from: http:///
ds32506/ds32508/ds32512 41 of 130 table 8-11. clad clock source settings clad[6:4] refclk clka clkb clkc clkd 000 don't care ds3 input e3 input sts-1 input low output 001 ds3 input ds3 output e3 output sts-1 output 77.76 or 19.44mhz output 010 e3 input ds3 output e3 output sts-1 output 77.76 or 19.44mhz output 011 sts-1 input ds3 output e3 output sts-1 output 77.76 or 19.44mhz output 100 77.76mhz input ds3 output e3 output sts-1 output 77.76 or 19.44mhz output 101 19.44mhz input ds3 output e3 output sts-1 output 77.76 or 19.44mhz output 110 38.88mhz input ds3 output e3 output sts-1 output 77.76 or 19.44mhz output 111 12.80mhz input ds3 output e3 output sts-1 output 77.76 or 19.44mhz output table 8-12. clad clock pin output settings clad[3:0]* clka pin clkb pin clkc pin clkd pin xxx0 low output xxx1 pll-a output - xx0x low output xx1x pll-b output x0xx low output x1xx pll-c output 0xxx low output 1xxx pll-d output * when clad[6:4] = 000, clka, clkb, and clkc are inputs and clkd is held low. 8.7.2 one-second reference generator the one-second reference signal can be used to update performance monitoring registers on a precise one- second interval. the generated internal signal is a 50% duty cycle signal that is divided down from the indicated reference signal. the low to high edge on this signal sets the global.srl :1srefl latched one-second bit, which can generate an interrupt if enabled. the low to high edge is used to initiate a performance monitor register update when global.cr1 :gpm[1:0] = 1x. the internal one-second reference can be output on the gpiob3 pin by setting global.cr1 :g1sroe. the source for the one second reference is set by global.cr1 :g1srs[3:0]. the ds3, e3, and sts-1 reference clocks are sourced from the clad, if the clad is configured to generate them, or from the clka, clkb ,and clkc pins, respectively. table 8-13. global one-s econd reference source g1srs[3:0] source 0000 disabled 0001 ds3 reference clock 0010 e3 reference clock 0011 sts-1 reference clock 0100 port 1 tclk 0101 port 2 tclk 0110 port 3 tclk 0111 port 4 tclk 1000 port 5 tclk 1001 port 6 tclk 1010 port 7 tclk 1011 port 8 tclk 1100 port 9 tclk 1101 port 10 tclk 1110 port 11 tclk 1111 port 12 tclk downloaded from: http:///
ds32506/ds32508/ds32512 42 of 130 8.7.3 general-purpose i/o pins when a microprocessor interface is enabled ( ifsel 000), there are two general-purpose i/o (gpio) pins available per port, each of which can be used as a general-p urpose input, general-purpose output, or loss-of-signal output. in addition, gpiob1, gpiob2, and gpiob3 can be used as a global i/o signal. the gpio pins are independently configurable using the gpio yn s fields of the global.gioacr and global.giobcr registers (see table 8-15 ). when a gpio pin is configured as an input, its value can be read from the global.gioarr or global.giobrr registers. when a gpio pins is configured as a loss-of-signal status output, its state mimics the state of the line.rsr :los status bit. when a port is powered down and a gpio pin has been programmed as an associated loss-of-signal output, the pin is held low. programming a gpio pin as a global signal overrides the i/o settings specified by the gpioyns field for that pin and c onfigures the pin as an input or an output as shown in table 8-14 . table 8-14. gpio pin global signal assignments global signal pin function control bit gpioa n none gpiob1 global pmu input global.cr1 .gpm[1:0] gpiob2 global tmei input global.cr1 .meims gpiob3 1sref output global.cr1 .g1sroe gpiob k none note: n = 1 to 12, k = 4 to 12. table 8-15. gpio pin control gpio yn s[1:0] function 00 input 01 output los status for port n 10 output logic 0 11 output logic 1 note: n = 1 to 12, y = a or b. 8.7.4 performance monitor register update each performance monitor counter can count at least one second of events before saturating at the maximum count. each counter has an associated status bit that is set when the counter value is not zero, a latched status bit that is set when the counter value changes from zero to one, and a latched status bit that is set each time the counter is incremented. there is a holding register for each performance moni tor counter that is updated when a performance monitoring update is performed. a performance monitoring update causes the counter value to be loaded into the holding register and the counter to be cleared. if a counter increment occurs at the exact same time as the counter reset, the counter is loaded with a value of one, and the counter is non-zero latched status bit is set. the performance monitor update (pmu) signal initiates a performance monitoring update. the pmu signal can be sourced from a general-purpose i/o pin (gpiob1), the internal one-second reference, a global register bit ( global.cr1 :gpmu), or a port register bit ( port.cr1 :pmu). note: the bert pmu can be sourced from a block level register bit ( bert.cr :lpmu). to use gpiob1, global.cr1 .gpm[1:0] is set to 01, the appropriate port.cr1 :pmum bits are set to 1, and the appropriate bert.cr :pmum bits are set to 1. to use the internal one- second reference, global.cr1 :gpm[1:0] is set to 1x, the appropriate port.cr1 :pmum bits are set to 1, and the appropriate bert.cr :pmum bits are set to 1. to use the global pmu register bit, global.cr1 :gpm[1:0] is set to 00, the appropriate port.cr1 :pmum bits are set to 1, and the appropriate bert.cr :pmum bits are set to 1. to use the port pmu register bit, the associated port.cr1 :pmum bit is set to 0, and the appropriate bert.cr :pmum bits are set to 1. to use the bert.cr :lpmu register bit, the appropriate bert.cr :pmum bit is set to 0. when using the global or port pmu register bits, the pmu bit should be set to initiate the process and cleared when the associated pms status bit ( global.sr :gpms or port.sr :pms) is set. when using the gpio pin or internal one-second reference, the pms bit is set shortly after the signal goes high, and cleared shortly after the signal downloaded from: http:///
ds32506/ds32508/ds32512 43 of 130 goes low. the pms has an associated latched status bit that can generate an interrupt if enabled. the port pms signal does not go high until an update of all the appropri ately configured block-level performance monitoring counters in the port has been completed. the global pms signal does not go high until an update of all the appropriately configured port-level performance monitoring counters in the entire chip has been completed. 8.7.5 transmit manual error insertion various types of errors can be inserted in the transm it data stream using the transmit manual error insertion (tmei) signal, which can be sourced from a block-level register bit, a port register bit ( port.cr1 :tmei), a global register bit ( global.cr1 :tmei), or a general-purpose i/o pin (gpiob2). to use gpiob2 as the tmei signal, global.cr1 .meims is set to 1, the appropriate port.cr1 .meims bits are set to 1, and the appropriate block- level meims bits are set to 1. to use the global tmei register bit, global.cr1 .meims is set to 0, the appropriate port.cr1 .meims bits are set to 1, and the appropriate block-le vel meims bits are set to 1. to use the port tmei register bit, the associated port.cr1 .meims is set to 0 and the appropriate bl ock-level meims bits are set to 1. to use the block-level tsei register bit, the associated block-level meims bit is set to 0. in order for an error of a particular type to be inserted, the error type must be enabled by setting the associated error insertion enable bit in the associated block's error insertion register. once enabled, a single error is inserted at the next opportunity when the tmei signal transitions from zero to one. note: if the tmei signal has multiple zero-to-one transitions between error insertion opportunities, only a single error is inserted. 8.8 8-/16-bit parallel mi croprocessor interface see table 11-8 and figure 11-3 to figure 11-10 for parallel interface timing diagrams and parameters. 8.8.1 8-bit and 16-bit bus widths when the ifsel pins are set to 1xx, the device presents a para llel microprocessor interface. in 8-bit modes ( ifsel = 10x), the address is composed of all the address bits including a[0] , the lower 8 data lines d[7:0] are used, and the upper 8 data lines d[15:8] are disabled (high impedance). in 16-bit modes ( ifsel = 11x), the address does not include a[0] , and all 16 data lines d[15:0] are used. 8.8.2 byte swap mode in 16-bit modes ( ifsel = 11x), the microprocessor interfac e can operate in byte swap mode. the bswap pin is used to determine whether byte swapping is enabled. this pin should be static and not change during operation. when the bswap pin is low the upper register bits reg[15:8] are mapped to the upper external data bus lines d[15:8], and the lower register bits reg[7:0] are mapped to the lower external data bus lines d [7:0]. when the bswap pin is high the upper register bits reg[15:8] are mapped to the lower external data bus lines d [7:0], and the lower register bits reg[7:0] are mapped to the upper external data bus lines d[15:8]. 8.8.3 read-write and data strobe modes the processor interface can operate in either read-write strobe mode (also known as "intel" mode) or data strobe mode (also known as "motorola" mode). when ifsel = 1x0 the read-write strobe mode is enabled. in this mode a negative pulse on rd performs a read cycle, and a negative pulse on wr performs a write cycle. when ifsel = 1x1 the data strobe mode is enabled. in this mode, a negative pulse on ds when r/w is high performs a read cycle, and a negative pulse on ds when r/w is low performs a write cycle. 8.8.4 multiplexed and nonmultiplexed operation in all parallel interface modes the interface suppor ts both multiplexed and nonmultiplexed operation. for multiplexed operation in 8-bit modes, wire a [10:8] to the processors a [10:8] pins, wire a [7:0] to d [7:0] and to the processors multiplexed address/data bus, and connect the ale pin to the appropriate pin on the processor. for nonmultiplexed 8-bit operation, wire ale high and wire a [10:0] and d [7:0] to the appropriate pins on the processor. for multiplexed operation in 16-bit modes, wire a [10:0] to d[10:0], wire d[15:0] to the cpus multiplexed address/data bus, and connect the ale pin to the appropriate pin on the processor. for nonmultiplexed 16-bit operation, wire ale high and wire a [10:0] and d[15:0] to the appropriate pins on the processor. downloaded from: http:///
ds32506/ds32508/ds32512 44 of 130 8.8.5 clear-on-read and clear-on-write modes the latched status register bits can be programmed to cl ear on a read access or clear on a write access. the global control register bit global.cr2 .lsbcre specifies the method used to clear all of the latched status registers. when lsbcre = 0, latched st atus register bits are cleared when written with a 1. when lsbcre = 1, latched status register bits are cleared when read. the clear-on-write mode expects the user to use the following method: read the latched status register then write a 1 to the register bits to be cleared. this method is useful when multiple software tasks use the same latched status register. each task can clear the bits it uses without affe cting any of the latched status bits used by other tasks. the clear-on-read mode clears all latched status bits in a r egister automatically when the latched status register is read. this method works well when no more than one softwar e task uses any single latched status register. an event that occurs while the associated latched status regi ster is being read results in the associated latched status bit being set after the read is completed. 8.8.6 global write mode when global.cr2 :gwrm = 1, a write to a register of any port causes the data to be written to the same register in all the ports on the device. in this mode register reads are not supported and result in undefined data. 8.9 spi serial microprocessor interface when the ifsel pins are set to 01x the device presents an spi interface on the cs , sclk , sdi , and sdo pins. spi is a widely-used master/slave bus protocol that a llows a master device and one or more slave devices to communicate over a serial bus. the ds325xx is always a slave device. masters are ty pically microprocessors, asics or fpgas. data transfers are always initiate d by the master device, which also generates the sclk signal. the ds325xx receives serial data on the sdi pin and transmits serial data on the sdo pin. sdo is high-impedance except when the ds325xx is transmitting data to the bus master. note that the ale pin must be wired high for proper operation of the spi interface. bit order. when ifsel[2:0] = 010 the register address and all data bytes are transmitted msb first on both sdi and sdo . when ifsel[2:0] = 011, the register address and all data bytes are transmitted lsb first on both sdi and sdo . the motorola spi convention is msb first. clock polarity and phase. the cpol pin defines the polarity of sclk . when cpol = 0, sclk is normally low and pulses high during bus transactions. when cpol = 1, sclk is normally high and pulses low during bus transactions. the cpha pin sets the phase (active edge) of sclk . when cpha = 0, data is latched in on sdi on the leading edge of the sclk pulse and updated on sdo on the trailing edge. when cpha = 1, data is latched in on sdi on the trailing edge of the sclk pulse and updated on sdo on the following leading edge. see figure 8-10 . device selection. each spi device has its own chip-select line. to select the ds325xx, pull its cs pin low. control word. after cs is pulled low, the bus master transmits the control word during the first 16 sclk cycles. in msb-first mode, the control word has the form: r/ w a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 burst where a[13:0] is the register address, r/ w is the data direction bit (1 = read, 0 = write), and burst is the burst bit (1 = burst access, 0 = single-byte access). in lsb-first mo de, the order of the 14 address bits is reversed. in the discussion that follows, a control word with r/ w = 1 is a read control word, while a control word with r/ w = 0 is a write control word. note: the address range of the ds32512 is 000hC7ffh, so a[13:11] are ignored. single-byte writes. see figure 8-11 . after cs goes low, the bus master transmits a write control word with burst = 0 followed by the data byte to be written. the bus master then terminates the transaction by pulling cs high. single-byte reads. see figure 8-11 . after cs goes low, the bus master transmits a read control word with burst = 0. the ds325xx then responds with the reques ted data byte. the bus master then terminates the transaction by pulling cs high. burst writes. see figure 8-11 . after cs goes low, the bus master transmits a write control word with burst = 1 followed by the first data byte to be written. the ds325xx receives the first data byte on sdi , writes it to the specified register, increments its inte rnal address register, and prepares to receive the next data byte. if the master downloaded from: http:///
ds32506/ds32508/ds32512 45 of 130 continues to transmit, the ds325xx continues to write t he data received and increment its address counter. after the address counter reaches 7ffh it rolls over to address 000h and continues to increment. burst reads. see figure 8-11 . after cs goes low, the bus master transmits a read control word with burst = 1. the ds325xx then responds with the requested data byte on sdo , increments its address counter, and prefetches the next data byte. if the bus master continues to demand data, the ds325xx continues to provide the data on sdo , increment its address counter, and prefetch the following byte. after the address counter reaches 7ffh it rolls over to address 000h and continues to increment. early termination of bus transactions. the bus master can terminate spi bus transactions at any time by pulling cs high. in response to early terminations, the ds325xx resets its spi interface logic and waits for the start of the next transaction. if a write transaction is terminated prior to the sclk edge that latches the lsb of a data byte, the current data byte is not written. design option: wiring sdi and sdo together. because communication between the bus master and the ds325xx is half-duplex, the sdi and sdo pins can be wired together externally to reduce wire count. to support this option, the bus master must not drive the sdi / sdo line when the ds325xx is transmitting. ac timing. see table 11-9 and figure 11-11 for ac timing specifications for the spi interface. figure 8-10. spi clock pola rity and phase options msb lsb 654321 cs sck sck sck sck sdi/sdo clock edge used for data capture (all modes) cpol = 0, cpha = 0 cpol = 0, cpha = 1 cpol = 1, cpha = 0 cpol = 1, cpha = 1 downloaded from: http:///
ds32506/ds32508/ds32512 46 of 130 figure 8-11. spi bus transactions r/ w register address burst data byte sdi cs sdo single-byte write single-byte read r/ w register address burst data byte r/ w register address burst data byte 1 burst write sdi cs sdo sdi cs sdo 0 (write) 0 (single-byte) 1 (read) 0 (single-byte) 0 (write) 1 (burst) data byte n r/ w register address burst data byte 1 burst read sdi cs 1 (read) 1 (burst) data byte n sdo 8.10 interrupt structure the interrupt structure is designed to efficiently guide the us er to the source of an interrupt. the status bits in the global interrupt status register ( global.isr ) are read to determine if the interrupt source comes from a global event, such as a one-second timer interrupt, or one of the ports. if the interrupt source is a global event, the global status register is read ( global.srl ) to determine the source. if the interrupt source is a port, the port interrupt status register ( port.isr ) is read to determine if the interrupt source comes from a port event, such as a performance monitor update interrupt, or one of the functional blocks inside the port. if the interrupt source is a port event, the port status register is read ( port.srl ) to determine the source. if the interrupt source is from a functional block inside the port, the associated block's stat us register is read to determine the source. the source of an interrupt can be determined by reading no more than three 16-bit registers. once the interrupt source has been determined, the interrupt can be clear ed by either reading or writing the latched status register (see section 8.8.5 ). an alternate method for clearing an interrupt is to disable the interrupt at the bit, block, port, or global level by writing a zero to the asso ciated interrupt enable bit. note: disabling the interrupt at the block, port, or global level disables all interrupts sources at or below that level. downloaded from: http:///
ds32506/ds32508/ds32512 47 of 130 figure 8-12. interrupt signal flow global latched status register and interrupt enable register int* global.srl bit global.srie bit global interrupt status register and interrupt enable register global.isr bit global.isrie bit block latched status register and interrupt enable register block srl bit block srie bit port interrupt status register and interrupt enable register port.isrie bit port.isr bit port.isr bit port.isrie bit port.srl bit port latched status register and interrupt enable register port.srie bit port.srl bit port.srie bit block srl bit block srie bit global.srl bit global.srie bit global.isrie bit global.isr bit 8.11 reset and power-down when only the hardware interface is enabled ( ifsel = 000 and hw = 1), the device is can be reset via the rst pin. the transmitters of all ports can be powered down using the tpd pin, while the receivers of all ports can be powered down using the rpd pin. when a microprocessor interface is enabled ( ifsel 000), the device presents a number of reset and power down options. the device can be reset at a global level via the global.cr1: rst bit or the rst pin, and at the port level via the port.cr1 :rst bit. each port can be powered down via the port.cr1 :tpd and rpd bits. the jtag logic is reset by the jtrst pin. the external rst pin and the global reset bit ( global.cr1 :rst) are combined to create an internal global reset signal. the global reset signal resets all the status and control registers on the chip (except the global.cr1 :rst bit), to their default values. it also resets all flip-flops in the global logic (including the clad block) and port logic to their reset values. the global.cr1 :rst bit stays set after a one is written to it. it is reset to zero when a zero is written to it or when the external rst pin is active. at the port level, the global reset signal combines with the port reset bit ( port.cr1 :rst) to create a port reset signal. the port reset signal resets all the status and control registers in the port (except port.cr1 :rst bit) to their default values. it also resets all flip-flops in the port logic to their reset values. the port reset bit ( port.cr1 :rst) stays set after a one is written to it. it is rese t to zero when a zero is written to it or when the global reset signal is active. the data path reset (rstdp) resets all of the same register s and flip-flops as the general reset (rst), except for the control registers. this allows the device to be programmed while the data path logic is in reset. it is recommended that a port be placed in data path reset during configuration changes. the global data path reset bit ( global.cr1 :rstdp) is set to one when the global reset signal is active. this bit is cleared when a zero is written to it while the global reset signal is inactive. the global data path reset resets all of the data path registers and flip-flops on the chip. the port data path reset bit ( port.cr1 :rstdp) is set to one when the port re set signal is acti ve. it is cleared when a zero is written to it while the port reset signal is inactive. the port data path reset resets all of the port logic data path registers and flip-flops. downloaded from: http:///
ds32506/ds32508/ds32512 48 of 130 table 8-16. reset and power-down sources register bits pin global.cr1 port.cr1 internal signals rst rst rstdp rst tpd rpd rstdp global reset global data path reset port reset tx port power- down rx port power- down port data path reset 0 f0 f1 f0 f1 f1 f1 1 1 1 1 1 1 1 1 f1 f0 f1 f1 f1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 1 f1 f1 f1 0 0 1 1 1 1 1 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 register bit states: f0 = forced to 0, f1 = forced to 1, 0 = set to 0, 1 = set to 1 the reset signals in the device are asserted asynchronously and do not require a clock to put the logic into the reset state. the control registers do not require a clock to come out of the reset state, but all other logic does require a clock to come out of the reset state. the port transmit power-down function ( port.cr1 :tpd) disables all the transmit clocks and powers down the transmit liu to minimize power consumption. the port receive power-down function ( port.cr1 :rpd) disables all of the receive clocks and powers down the receive li u to minimize power consumption. the one-second timer circuit can be powered down by disabling its reference clock. the clad can be powered down by disabling it (setting global.cr2 :clad[6:0] = 0). the global logic cannot be powered down. after a global reset, all of the control and status registers in all ports are set to their default values and all the other flip-flops are reset to their reset values. the global data path reset ( global.cr1 :rstdp), all the port data path resets ( port.cr1 :rstdp), and all the port power-down ( port.cr1 :tpd and rpd) bits are set after the global reset. a valid initialization sequence is to clear the port power-down bits in the ports that are to be active, write to all of the configuration registers to set them in the desired modes, then clear the global.cr1 :rstdp and port.cr1 :rstdp bits. this causes all the logic to start up in a predictable manner. the device can also be initialized by clearing the global.cr1 :rstdp, port.cr1 :rstdp, and port.cr1 :tpd and rpd bits, then writing to all of the configuration registers to set them in the desired modes, and then clearing all of the latched status bits. this second initialization scheme can caus e the device to operate unpredictably for a brief period of time. some of the i/o pins are put into a known state at rese t. at the global level, the microprocessor interface output and i/o pins ( d[15:0] ) are forced into the high impedance state when the rst pin is active, but not when the global.cr1 :rst bit is active. the clad clock pins clka , clkb , and clkc are forced to be the liu reference clock inputs. the general-purpose i/o pins ( gpioan and gpiobn ) are forced to be inputs until after the rst pin is deasserted. at the port level, the liu transmitter outputs txp and txn are forced into a high-impedance state. note: setting any of the reset (rst), data path reset (rstdp), or power-down (tpd, rpd) bits for less than 100 ns may result in the associated circuits coming up in a random state. when a power-down bit is cleared, it takes approximately 1ms for all of the as sociated circuits to power-up. downloaded from: http:///
ds32506/ds32508/ds32512 49 of 130 9. register maps and descriptions 9.1 overview when a microprocessor interface is enabled ( ifsel[2:0] 000), the registers described in this section are accessible. the overall memory map is shown in table 9-1 . the ds32512 register map covers the address range of 000 to 7ffh. on the ds32508, writes in the address space for lius 9 through 12 are ignored, and reads from these addresses return 00h. on the ds32506, address line a [10] is not present, and writes into the address space for liu 7 are ignored, and reads from these addresses return 00h. the address lsb a[0] is used to address the upper and lower bytes of a register in 8-bit mode, and to swap the upper and lower bytes in 16-bit mode. in each register, bit 15 is the msb and bit 0 is the lsb. register addresses not listed and bits marked are reserved and must be written with 0 and ignored when read. writing other values to these registers may put the device in a factory test mode resulting in undefined operation. bits labeled 0 or 1 must be written with that value for proper operation. register fields with underlined names are read-only fields; writes to these fields have no effect. all other fields are read-write. register fields are described in detail in the register descriptions in sections 9.3 to 9.8 . 9.1.1 status bits the device has two types of status bits. real-time status bits are read-only and indicate the state of a signal at the time it is read. latched status bit are set when the associated event occurs and remain set until cleared. once cleared, a latched status bit is not set again until the associated event recurs (goes away and comes back). a latched-on-change bit is a latched status bit that is set when the event occurs and when it goes away. a latched status bit can be cleared using either a clear- on-read or clear-on-write method (see section 8.8.5 ). for clear-on- read, all latched status bits in a latched status register ar e cleared when the register is read. in 16-bit mode, all 16 latched status bits are cleared. in 8-bit mode, only the eight bits read are cleared. for clear-on-write, a latched bit in a latched status register is cleared when a logic 1 is wri tten to that bit. for example, writing ffffh to a 16-bit latched status register clears all latched status bits in the register, whereas writing 0001h only clears bit 0 of the register. when set, some latched status bits can cause an interrupt request if enabled to do so by corresponding interrupt enable bits. 9.1.2 configuration fields configuration fields are read-write. during reset, each conf iguration field reverts to the default value shown in the register definition. configuration register bits marked are reserved and must be written with 0. configuration registers and bits can be written to and read from duri ng a data path reset, however, all changes to these bits are ignored during the data path reset. as a result, all bits requiring a zero-to-one transition to initiate an action must have the transition occur after the data path reset has been removed. see section 8.11 for more information about resets and data path resets. 9.1.3 counters all counters stop counting at their maximum count. a count er register is updated by asserting (low to high transition) the performance monitoring update signal (pmu ). during a counter register update, the performance monitoring status signal (pms) is deasserted. a counter register update consists of loading the counter register with the current count, resetting the counter, resetting the zero count status indication, and then asserting pms. no events are missed during an update. see section 8.7.4 for more information about performance monitor register updates. downloaded from: http:///
ds32506/ds32508/ds32512 50 of 130 9.2 overall register map table 9-1. overa ll register map base address block 000h global registers 080h port registers for port 1 100h port registers for port 2 180h port registers for port 3 200h port registers for port 4 280h port registers for port 5 300h port registers for port 6 380h port registers for port 7 400h port registers for port 8 480h port registers for port 9 500h port registers for port 10 580h port registers for port 11 600h port registers for port 12 680h unused table 9-2. port registers address offset description block 00hC1fh port common registers port 20hC2fh liu registers liu 30hC3fh b3zs/hdb3 encoder registers line tx 40hC4fh b3zs/hdb3 decoder registers line rx 50hC6fh bert registers bert 70hC7fh unused note: the address offsets given in this table are offsets from port base addresses shown in table 9-1 . downloaded from: http:///
ds32506/ds32508/ds32512 51 of 130 9.3 global registers table 9-3. globa l register map address offset register register description 000h global.idr id register 002h global.cr1 global control register 1 004h global.cr2 global control register 2 006hC00eh unused 010h global.gioacr1 general-purpose i/o a control register 1 012h global.gioacr2 general-purpose i/o a control register 2 014h global.giobcr1 general-purpose i/o b control register 1 016h global.giobcr2 general-purpose i/o b control register 2 018hC01eh unused 020h global.isr global interrupt status register 022h global.isrie global interrupt enable register 024hC026h unused 028h global.sr global status register 02ah global.srl global status register latched 02ch global.srie global status register interrupt enable 02ehC036h unused 038h global.gioarr general-purpose i/o a read register 03ah global.giobrr general-purpose i/o b read register 03chC07eh unused register name: global.idr register description: id register register address: 000h bit # 15 14 13 12 11 10 9 8 name id15 id14 id13 id12 id11 id10 id9 id8 bit # 7 6 5 4 3 2 1 0 name id7 id6 id5 id4 id3 id2 id1 id0 bits 15 to 12: device rev id (id[15:12]). these bits of the device id register have the same information as the four bits of the jtag rev id portion of the jtag id register, jtag id[31:28]. see section 10 . bits 11 to 0: device code id (id[11:0]). these bits of the device id register have the same information as the 12 bits of the jtag code id portion of the jtag id register, jtag id[23:12]. see section 10 . downloaded from: http:///
ds32506/ds32508/ds32512 52 of 130 register name: global.cr1 register description: global control register #1 register address: 002h bit # 15 14 13 12 11 10 9 8 name g1srs[3:0] g1sroe default 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name tmei meims gpm[1:0] gpmu rstdp rst default 0 0 0 0 0 0 1 0 bits 12 to 9: global one-second reference source (g1srs[3:0]). these bits determine the source for the internally generated one second reference. the source is se lected from one of the clad clocks or from one of the port transmit clocks. see section 8.7.2 . 0000 = disabled 0001 = ds3 reference clock 0010 = e3 reference clock 0011 = sts-1 reference clock 0100 = port 1 tclk 0101 = port 2 tclk 0110 = port 3 tclk 0111 = port 4 tclk 1000 = port 5 tclk 1001 = port 6 tclk 1010 = port 7 tclk 1011 = port 8 tclk 1100 = port 9 tclk 1101 = port 10 tclk 1110 = port 11 tclk 1111 = port 12 tclk bit 8: global one-second reference output enable (g1sroe). this bit determines whether the gpiob3 pin is used to output the global one second reference signal. see section 8.7.2 . 0 = gpiob3 pin mode selected by global.giobcr1 :giob3s[1:0]. 1 = gpiob3 outputs the global one second reference signal specified by global.cr1 :g1srs[3:0] bit 7: transmit manual error insert (tmei). when global.cr1 :meims = 0, this bit is used to insert errors in all blocks in all ports where block-level meims = 1 and port.cr1 :meims = 1. error(s) are inserted at the next opportunity after this bit transitions from low to high. see section 8.7.5 . note: this bit should be set low immediately after each error insertion. bit 6: manual error inser t mode select (meims). this bit specifies the source of the manual error insertion signal for all block-level error generators that have block-level meims = 1 and port.cr1 :meims = 1. see section 8.7.5 . 0 = global error insertion using global.cr1 :tmei bit 1 = global error insertion using the gpiob2 pin bits 5 and 4: global performance monitor update mode (gpm[1:0]). these bits specify the source of the performance monitoring update signal for all blocks that have block-level pmum = 1 and port.cr1 :pmum = 1. see section 8.7.4 . 00 = global pm update using the global.cr1 :gpmu bit 01 = global pm update using the gpiob1 pin 1x = one-second pm update using the internal one-second counter (see section 8.7.2 ) downloaded from: http:///
ds32506/ds32508/ds32512 53 of 130 bit 3: global performance monitor register update (gpmu). when global.cr1 :gpm[1:0] = 00, this bit is used to update all of the performance monitor registers where block-level pmum = 1 and port.cr1 :pmum = 1. when this bit transitions from low to high, all configur ed performance monitoring registers are updated with the latest counter value, and all associated counters are reset. this bit should remain high until the performance monitor update status bit ( global.sr :gpms) goes high, and then it should be brought back low, which clears the gpms status bit. if a counter increment occurs at the exact same time as the counter reset, the counter is loaded with a value of one, and the counter is non-zero latched status bit is set. see section 8.7.4 . bit 1: reset data path (rstdp). when this bit is set, it forces all of the internal data path and status registers in all ports to their default state. this bit must be set high for a minimum of 100ns. see section 8.11. 0 = normal operation 1 = force all data path registers to their default values bit 0: reset (rst). when this bit is set, all of the internal data path and status and control registers (except this rst bit), on all of the ports, are reset to their default stat e. this bit must be set high for a minimum of 100ns. this bit is logically ored with the inverted hardware signal rst . see section 8.11 . 0 = normal operation 1 = force all internal registers to their default values downloaded from: http:///
ds32506/ds32508/ds32512 54 of 130 register name: global.cr2 register description: global control register #2 register address: 004h bit # 15 14 13 12 11 10 9 8 name clad[6:0] default 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name clkd19 intm ras rad lsbcre gwrm default 0 0 0 0 0 0 0 0 bits 14 to 8: clad i/o mode (clad[6:0]). these bits control the clad clock i/o pins refclk , clka , clkb , clkc and clkd . see table 8-11 and table 8-12 in section 8.7.1 . bit 5: clkd frequency is 19.44mhz (clkd19). this bit specifies the frequency to be output on clkd when the clad[3] configuration bit is high. 0 = 77.76mhz 1 = 19.44mhz bit 4: int pin mode (intm). this bit determines the inactive mode of the int pin. the int pin always drives low when an enabled interrupt source is active. see section 8.10 . 0 = pin is high impedance when no enabled interrupts are active 1 = pin drives high when no enabled interrupts are active bit 3: rdy/ ack select (ras). this bit controls the microprocessor interface output pin rdy/ack in intel mode (ifsel = 100 or 110) and motorola mode (ifsel = 101 or 111). 0 = normal operation: rdy in intel mode and ack in motorola mode 1 = reverse operation: ack in intel mode and rdy in motorola mode bit 2: rdy/ ack disable (rad). this bit disables the microprocessor interface output pin rdy/ack . 0 = enable, normal operation 1 = disable, tri-state bit 1: latched status bit clear-on-read enable (lsbcre). this bit determines when the latched status register bits are cleared. see section 8.8.5 . 0 = latched status register bits are cleared on a write 1 = latched status register bits are cleared on a read bit 0: global write mode (gwrm). this bit enables the global write mode. when this bit is set, a write to a register of any port causes a write to the same register in all the ports. in this mode register reads are not supported and result in undefined data. see section 8.8.6 . 0 = normal write mode 1 = global write mode downloaded from: http:///
ds32506/ds32508/ds32512 55 of 130 register name: global.gioacr1 register description: general-purpose i/o a control register #1 register address: 010h bit # 15 14 13 12 11 10 9 8 name gioa8s[1:0] gioa7s[1:0] gioa6s[1:0] gioa5s[1:0] default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name gioa4s[1:0] gioa3s[1:0] gioa2s[1:0] gioa1s[1:0] default 0 0 0 0 0 0 0 0 note: see section 8.7.3 for more information. bits 15, 14: general-purpose i/o a 8 select (gioa8s[1:0]). these bits specify the function of the gpioa8 pin. 00 = input 01 = output los status for port 8 10 = output logic 0 11 = output logic 1 bits 13, 12: general-purpose i/o a 7 select (gioa7s[1:0]). these bits specify the function of the gpioa7 pin. 00 = input 01 = output los status for port 7 10 = output logic 0 11 = output logic 1 bits 11, 10: general-purpose i/o a 6 select (gioa6s[1:0]). these bits specify the function of the gpioa6 pin. 00 = input 01 = output los status for port 6 10 = output logic 0 11 = output logic 1 bits 9, 8: general-purpose i/o a 5 select (gioa5s[1:0]). these bits specify the function of the gpioa5 pin. 00 = input 01 = output los status for port 5 10 = output logic 0 11 = output logic 1 bits 7, 6: general-purpose i/o a 4 select (gioa4s[1:0]). these bits specify the function of the gpioa4 pin. 00 = input 01 = output los status for port 4 10 = output logic 0 11 = output logic 1 bits 5, 4: general-purpose i/o a 3 select (gioa3s[1:0]). these bits specify the function of the gpioa3 pin 00 = input 01 = output los status for port 3 10 = output logic 0 11 = output logic 1 bits 3, 2: general-purpose i/o a 2 select (gioa2s[1:0]). these bits specify the function of the gpioa2 pin. 00 = input 01 = output los status for port 2 10 = output logic 0 11 = output logic 1 bits 1, 0: general-purpose i/o a 1 select (gioa1s[1:0]). these bits specify the function of the gpioa1 pin. 00 = input 01 = output los status for port 1 10 = output logic 0 11 = output logic 1 downloaded from: http:///
ds32506/ds32508/ds32512 56 of 130 register name: global.gioacr2 register description: general-purpose i/o a control register #2 register address: 012h bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name gioa12s[1:0] gioa11s[1:0 ] gioa10s[1:0] gioa9s[1:0] default 0 0 0 0 0 0 0 0 note: see section 8.7.3 for more information. bits 7, 6: general-purpose i/o a 12 select (gioa12s[1:0]). these bits specify the function of the gpioa12 pin. 00 = input 01 = output los status for port 12 10 = output logic 0 11 = output logic 1 bits 5, 4: general-purpose i/o a 11 select (gioa11s[1:0]). these bits specify the function of the gpioa11 pin 00 = input 01 = output los status for port 11 10 = output logic 0 11 = output logic 1 bits 3, 2: general-purpose i/o a 10 select (gioa10s[1:0]). these bits specify the function of the gpioa10 pin. 00 = input 01 = output los status for port 10 10 = output logic 0 11 = output logic 1 bits 1, 0: general-purpose i/o a 9 select (gioa9s[1:0]). these bits specify the function of the gpioa9 pin. 00 = input 01 = output los status for port 9 10 = output logic 0 11 = output logic 1 downloaded from: http:///
ds32506/ds32508/ds32512 57 of 130 register name: global.giobcr1 register description: general-purpose i/o b control register #1 register address: 014h bit # 15 14 13 12 11 10 9 8 name giob8s[1:0] giob7s[1:0] giob6s[1:0] giob5s[1:0] default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name giob4s[1:0] giob3s[1:0] giob2s[1:0] giob1s[1:0] default 0 0 0 0 0 0 0 0 note: see section 8.7.3 for more information. bits 15, 14: general-purpose i/o b 8 select (giob8s[1:0]). these bits specify the function of the gpiob8 pin. 00 = input 01 = output los status for port 8 10 = output logic 0 11 = output logic 1 bits 13, 12: general-purpose i/o b 7 select (giob7s[1:0]). these bits specify the function of the gpiob7 pin. 00 = input 01 = output los status for port 7 10 = output logic 0 11 = output logic 1 bits 11, 10: general-purpose i/o b 6 select (giob6s[1:0]). these bits specify the function of the gpiob6 pin. 00 = input 01 = output los status for port 6 10 = output logic 0 11 = output logic 1 bits 9, 8: general-purpose i/o b 5 select (giob5s[1:0]). these bits specify the function of the gpiob5 pin. 00 = input 01 = output los status for port 5 10 = output logic 0 11 = output logic 1 bits 7, 6: general-purpose i/o b 4 select (giob4s[1:0]). these bits specify the function of the gpiob4 pin. 00 = input 01 = output los status for port 4 10 = output logic 0 11 = output logic 1 bits 5, 4: general-purpose i/o b 3 select (giob3s[1:0]). these bits specify the function of the gpiob3 pin. note: if global.cr1 :g1sroe is set to 1, gpiob3 is the global one second reference output signal. 00 = input 01 = output los status for port 3 10 = output logic 0 11 = output logic 1 bits 3, 2: general-purpose i/o b 2 select (giob2s[1:0]). these bits specify the function of the gpiob2 pin. note: if global.cr1 :meims is set to 1, gpiob2 is the global tran smit manual error insertion (tmei) input signal. 00 = input 01 = output los status for port 2 10 = output logic 0 11 = output logic 1 downloaded from: http:///
ds32506/ds32508/ds32512 58 of 130 bits 1, 0: general-purpose i/o b 1 select (giob1s[1:0]). these bits specify the function of the gpiob1 pin. note: if global.cr1 :gpm[1:0] is set to 01, gpiob1 is the global performance monitoring update input signal. 00 = input 01 = output los status for port 1 10 = output logic 0 11 = output logic 1 register name: global.giobcr2 register description: general-purpose i/o b control register #2 register address: 016h bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name giob12s[1:0] giob11s[1:0 ] giob10s[1:0] giob9s[1:0] default 0 0 0 0 0 0 0 0 note: see section 8.7.3 for more information. bits 7, 6: general-purpose i/o 12 select (giob12s[1:0]). these bits specify the function of the gpiob12 pin. 00 = input 01 = output los status for port 12 10 = output logic 0 11 = output logic 1 bits 5, 4: general-purpose i/o 11 select (giob11s[1:0]). these bits specify the function of the gpiob11 pin 00 = input 01 = output los status for port 11 10 = output logic 0 11 = output logic 1 bits 3, 2: general-purpose i/o 10 select (giob10s[1:0]). these bits specify the function of the gpiob10 pin. 00 = input 01 = output los status for port 10 10 = output logic 0 11 = output logic 1 bits 1, 0: general-purpose i/o 9 select (giob9s[1:0]). these bits specify the function of the gpiob9 pin. 00 = input 01 = output los status for port 9 10 = output logic 0 11 = output logic 1 downloaded from: http:///
ds32506/ds32508/ds32512 59 of 130 register name: global.isr register description: global interrupt status register register address: 020h bit # 15 14 13 12 11 10 9 8 name p12isr p11isr p10isr p9isr p8isr bit # 7 6 5 4 3 2 1 0 name p7isr p6isr p5isr p4isr p3isr p2isr p1isr gsr bits 12 to 1: port n interrupt status register (pnisr). this bit is set when any of the bits in the port n interrupt status register ( port.isr ) are set and enabled for interrupt. when set, this bit causes an interrupt if global.isrie :pnisrie is set. see section 8.10 . bit 0: global status register (gsr). this bit is set when any of the latched status register bits in the global latched status register ( global.srl ) are set and enabled for interrupt. when set, this bit causes an interrupt if global.isrie :gsrie is set. see section 8.10 . register name: global.isrie register description: global interrupt status register interrupt enable register address: 022h bit # 15 14 13 12 11 10 9 8 name p12isrie p11isrie p10isrie p9isrie p8isrie default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name p7isrie p6isrie p5isrie p4is rie p3isrie p2isrie p1isrie gsrie default 0 0 0 0 0 0 0 0 bits 12 to 1: port n interrupt status register interrupt enable (pnisrie). this bit is the interrupt enable for the global.isr :pnisr status bit. see section 8.10 . 0 = mask the interrupt 1 = enable the interrupt bit 0: global status register interrupt enable (gsrie). this bit is the interrupt enable for the global.isr :gsr status bit. see section 8.10 . 0 = mask the interrupt 1 = enable the interrupt downloaded from: http:///
ds32506/ds32508/ds32512 60 of 130 register name: global.sr register description: global status register register address: 028h bit # 15 14 13 12 11 10 9 8 name default bit # 7 6 5 4 3 2 1 0 name clol gpms default 0 0 bit 2: clad loss of lock (clol). this bit is set when the clad is not locked to the reference frequency. bit 0: global performance monitoring update status (gpms). this bit is set when the port.sr :pms status bits are set in all of the ports that are enabled for global update control (i.e., all ports that have port.cr1 :pmum = 1). ports that have port.cr1 :pmum = 0 have no effect on this bit. in global software update mode, the global update request bit ( global.cr1 :gpmu) should be held high until this status bit goes high. see section 8.7.4 . 0 = the associated update request signal is low or not all register updates are completed. 1 = the requested performance register updates are all completed. register name: global.srl register description: global status register latched register address: 02ah bit # 15 14 13 12 11 10 9 8 name bit # 7 6 5 4 3 2 1 0 name clkcl clkbl clkal cladl cloll g1srefl gpmsl bit 6: clad c clock activity latched (clkcl). this bit is set when the signal on the clkc pin is active. note: this bit should always be low when global.cr2 :clad[6:4] 000. see section 8.7.1 . bit 5: clad b clock activity latched (clkbl). this bit is set when the signal on the clkb pin is active. note: this bit should always be low when global.cr2 :clad[6:4] 000. see section 8.7.1 . bit 4: clad a clock activity latched (clkal). this bit is set when the signal on the clka pin is active. note: this bit should always be low when global.cr2 :clad[6:4] 000. see section 8.7.1 . bit 3: clad reference clock activity status latched (cladl). this bit is set when the clad pll reference clock signal on the refclk pin is active. note: when global.cr2 :clad[6:4] = 000, the refclk pin is unused. see section 8.7.1 . bit 2: clad loss of lock latched (cloll). this bit is set when the global.sr :clol status bit transitions from low to high. bit 1: global one-second status latched (g1srefl). this bit is set once each second when the internal global one-second timer signal transitions low to high. when set, this bit causes an interrupt if interrupt enables global.srie :g1srefie and global.isrie :gsrie are both set. see section 8.7.1 . bit 0: global performance monitoring update status latched (gpmsl). this bit is set when the global.sr :gpms status bit changes from low to high. when set, this bit causes an interrupt if interrupt enables global.srie :gpmsie and global.isrie :gsrie are both set. see section 8.7.1 . downloaded from: http:///
ds32506/ds32508/ds32512 61 of 130 register name: global.srie register description: global status register interrupt enable register address: 02ch bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name clolie g1srefie gpmsie default 0 0 0 0 0 0 0 0 bit 2: clad loss of lock interrupt enable (clolie). this bit is the interrupt enable for the global.srl :cloll bit. 0 = mask the interrupt 1 = enable the interrupt bit 1: global one-second interrupt enable (g1srefie). this bit is the interrupt enable for the global.srl :g1srefl bit. 0 = mask the interrupt 1 = enable the interrupt bit 0: global performance monitoring update status interrupt enable (gpmsie). this bit is the interrupt enable for the global.srl : gpmsl bit. 0 = mask the interrupt 1 = enable the interrupt register name: global.gioarr register description: general-purpose i/o a read register register address: 038h bit # 15 14 13 12 11 10 9 8 name gpioa12 gpioa11 gpioa10 gpioa9 bit # 7 6 5 4 3 2 1 0 name gpioa8 gpioa7 gpioa6 gpioa5 gpioa4 gpioa3 gpioa2 gpioa1 bits 11 to 0: general-purpose i/o a n status (gpioan). bit n indicates the status of general-purpose i/o a pin n (gpioan). see section 8.7.3 . register name: global.giobrr register description: general-purpose i/o b read register register address: 03ah bit # 15 14 13 12 11 10 9 8 name gpiob12 gpiob11 gpiob10 gpiob9 bit # 7 6 5 4 3 2 1 0 name gpiob8 gpiob7 gpiob6 gpiob5 gpiob4 gpiob3 gpiob2 gpiob1 bits 11 to 0: general-purpose i/o b n status (gpiobn). bit n indicates the status of general-purpose i/o b pin n (gpiobn). see section 8.7.3 . downloaded from: http:///
ds32506/ds32508/ds32512 62 of 130 9.4 port common registers table 9-4. port common register map address offset register register description 00h port.cr1 port control register 1 02h port.cr2 port control register 2 04h port.cr3 port control register 3 06h unused 08h unused 0ah port.inv port i/o invert control register 0ch unused 0eh unused 10h port.isr port interrupt status register 12h unused 14h port.isrie port interrupt status register interrupt enable 16h unused 18h port.sr port status register 1ah port.srl port status register latched 1ch port.srie port status register interrupt enable 1eh unused register name: port.cr1 register description: port control register 1 register address: n * 80h + 00h bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name tmei meims pmum pmu tpd rpd rstdp rst default 0 0 0 0 1 1 1 0 bit 7: transmit manual error insert (tmei). when port.cr1 :meims = 0, this bit is used to insert errors in all blocks where block-level meims = 1. error(s) are inserted at the next opportunity after this bit transitions from low to high. see section 8.7.5 . note: this bit should be set low immediately after each error insertion. bit 6: transmit manual error insert mode select (meims). this bit specifies the source of the error insertion signal for all block-level error generators that have block-level meims = 1. see section 8.7.5 . 0 = port-level error insertion via port.cr1 :tmei 1 = global error insertion as specified by global.cr1 :meims bit 5: port performance monitor update mode (pmum). this bit specifies the s ource of the performance monitoring update signal for all blocks that have block-level pmum = 1. see section 8.7.4 . 0 = port-level pm update via port.cr1 :pmu 1 = global pm update as specified by global.cr1 :gpm[1:0] bit 4: port performance monitor register update (pmu). when port.cr1 :pmum = 0, this bit is used to update all of the performance monitor registers where block-le vel pmum = 1. when this bit transitions from low to high, all configured performance monitoring registers are updated with the latest counter values, and all associated counters are reset. this bit should remain high until the performance monitor update status bit ( port.sr :pms) goes high, and then it should be brought back low, which cl ears the pms status bit. if a counter increment occurs at the exact same time as the counter reset, the counter is loaded with a value of one, and the counter is non- zero latched status bit is set. see section 8.7.4 . downloaded from: http:///
ds32506/ds32508/ds32512 63 of 130 bit 3: transmit power-down (tpd). when this bit is set, the transmit path of the port is powered down and considered out of service. the digital logic is powered down by stopping the clocks. see section 8.11 . 0 = normal operation 1 = power down the port transmit path ( txp and txn become high impedance) bit 2: receive power-down (rpd). when this bit is set, the receive path of the port is powered down and considered out of service. the digital logic is powered down by stopping the clocks. see section 8.11 . 0 = normal operation 1 = power down the port receive path ( rpos / rdat , rneg / rlcv , and rclk become high impedance) bit 1: reset data path (rstdp). when this bit is set, it forces all of the ports internal data path and status registers to their default state. this bit must be set hi gh for a minimum of 100ns and then set back low. see section 8.11. 0 = normal operation 1 = force all data path registers to their default values bit 0: reset (rst). when this bit is set, all of the internal data path and status and control registers (except this rst bit) of this port are reset to their default state. th is bit must be set high for a minimum of 100ns. this bit is logically ored with the inverted hardware signal rst and the global.cr1 :rst bit. see section 8.11 . 0 = normal operation 1 = force all internal registers to their default values downloaded from: http:///
ds32506/ds32508/ds32512 64 of 130 register name: port.cr2 register description: port control register 2 register address: n * 80h + 02h bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name lm[1:0] rod tbin rbin tcc default 0 0 0 0 0 0 0 0 bits 7 and 6: liu mode (lm[1:0]). these bits select the operating mode of the port. see section 8.1 . 00 = ds3 01 = e3 10 = sts-1 11 = reserved bit 4: receive output disable (rod). see section 8.3.6.4 . 0 = enable the receiver outputs 1 = disable the receiver outputs ( rclk , rpos / rdat , and rneg / rlcv ) bit 3: transmit binary interface enable (tbin). see section 8.2.2 . 0 = transmitter framer interface is bipolar on the tpos and tneg pins. the b3zs/hdb3 encoder is disabled. 1 = transmitter framer interface is binary on the tdat pin. the b3zs/hdb3 encoder is enabled. bit 2: receive binary interface enable (rbin). see section 8.3.6 . 0 = receiver framer interface is bipolar on the rpos and rneg pins. the b3zs/hdb3 decoder is disabled. 1 = receiver framer interface is binary on the rdat pin with the rlcv pin indicating line-code violations. the b3zs/hdb3 encoder is enabled. bit 1: transmit common clock mode (tcc). see section 8.2.1.1 . 0 = source transmit clock for port n from tclkn 1 = source transmit clock for port n from tclk1 downloaded from: http:///
ds32506/ds32508/ds32512 65 of 130 register name: port.cr3 register description: port control register 3 register address: n * 80h + 04h bit # 15 14 13 12 11 10 9 8 name berte bertd default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name scrd aist tais lbs lb[1:0] default 0 0 0 0 0 0 0 0 bit 9: bert enable (berte). see section 8.5 . 0 = disable the bert pattern generator (the pattern detector is always enabled) 1 = enable the bert pattern generator (the pattern detector is always enabled) bit 8: bert direction (bertd). see section 8.5 . 0 = line direction (transmit to receive) 1 = system direction (receive to transmit) bit 7: sts-1 scrambling disable (scrd). this bit controls sts-1 scrambling when ais-l is generated in sts-1 mode. see section 8.2.3 . 0 = perform scrambling 1 = do not perform scrambling bit 4: ais type (aist). see section 8.2.4 . 0 = unframed all ones 1 = framed ds3 ais (ds3 mode), unframed a ll ones (e3 mode), or ais-l (sts-1 mode) bit 3: transmit ais (tais). the type of ais signal depends on the liu mode (ds3, e3, or sts-1) and the configured ais type. see section 8.2.4 . 0 = transmit normal data 1 = transmit ais signal bit 2: loopback select (lbs). this bit affects the function of the loopback mode (lbm[1:0]) bits. bits 1 and 0: loopback mode (lb[1:0]). these bits enable loopbacks. the effect of the lb = 11 decode is controlled by the lbs configuration bit. see section 8.6 . 00 = no loopback 01 = diagnostic loopback (dlb) 10 = line loopback (llb) 11 (lbs = 0) = line loopback (llb) and diagnostic loopback (dlb) simultaneously 11 (lbs = 1) = analog loopback (alb) downloaded from: http:///
ds32506/ds32508/ds32512 66 of 130 register name: port.inv register description: port i/o invert control register register address: n * 80h + 0ah bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name tnegi tposi tclki rnegi rposi rclki default 0 0 0 0 0 0 0 0 bit 6: tneg invert (tnegi). this bit inverts the tneg input pin when set. 0 = noninverted 1 = inverted bit 5: tpos/tdat invert (tposi). this bit inverts the tpos / tdat input pin when set. 0 = noninverted 1 = inverted bit 4: tclk invert (tclki). this bit inverts the tclk pin input pin when set. see section 8.2.1 . 0 = noninverted; tpos / tdat and tneg are sampled on the rising edge of tclk . 1 = inverted; tpos / tdat and tneg are sampled on the falling edge of tclk . bit 2: rneg/rlcv invert (rnegi). this bit inverts the rneg / rlcv output pin when set. 0 = noninverted 1 = inverted bit 1: rpos/rdat invert (rposi). this bit inverts the rpos / rdat output pin when set. 0 = noninverted 1 = inverted bit 0: rclk invert (rclki). this bit inverts the rclkn output pin when set. see section 8.3.6.3 . 0 = noninverted; rpos / rdat and rneg / rlcv are updated on the falling edge of rclk . 1 = inverted; rpos / rdat and rneg / rlcv are updated on the rising edge of rclk . downloaded from: http:///
ds32506/ds32508/ds32512 67 of 130 register name: port.isr register description: port interrupt status register register address: n * 80h + 10h bit # 15 14 13 12 11 10 9 8 name bit # 7 6 5 4 3 2 1 0 name ldsr liusr bsr psr bit 3: line decoder status register interrupt status (ldsr). this bit is set when any of the latched status register bits in the b3zs/hdb3 line decoder block are set and enabled for interrupt. when set, this bit causes an interrupt if port.isrie :ldsrie and global.isrie :pnisrie are both set. see section 8.10 . bit 2: liu status register interrupt status (liusr). this bit is set when any of the latched status register bits in the liu block are set and enabled for interrupt. when set, this bit causes an interrupt if port.isrie :liusrie and global.isrie : pnisrie are both set. see section 8.10 . bit 1: bert status register interrupt status (bsr). this bit is set when any of the latched status register bits in the bert block are set and enabled for interrupt. when set, this bit causes an interrupt if port.isrie :bsrie and global.isrie : pnisrie are both set. see section 8.10 . bit 0: port status register interrupt status (psr). this bit is set when any of the latched status register bits in the port latched status register ( port.srl ) are set and enabled for interrupt. when set, this bit causes an interrupt if port.isrie :psrie and global.isrie : pnisrie are both set. see section 8.10 . register name: port.isrie register description: port interrupt status re gister interrupt enable register address: n * 80h + 14h bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name ldsrie liusrie bsrie psrie default 0 0 0 0 0 0 0 0 bit 3: line decoder status register interrupt enable (ldsrie). this bit is the interrupt enable for the port.isr :ldsr status bit. 0 = mask the interrupt 1 = enable the interrupt bit 2: liu status register interrupt enable (liusrie). this bit is the interrupt enable for the port.isr :liusr status bit. 0 = mask the interrupt 1 = enable the interrupt bit 1: bert status register interrupt enable (bsrie). this bit is the interrupt enable for the port.isr :bsr status bit. 0 = mask the interrupt 1 = enable the interrupt bit 0: port status register interrupt enable (psrie). this bit is the interrupt enable for the port.isr :psr status bit. 0 = mask the interrupt 1 = enable the interrupt downloaded from: http:///
ds32506/ds32508/ds32512 68 of 130 register name: port.sr register description: port status register register address: n * 80h + 18h bit # 15 14 13 12 11 10 9 8 name default bit # 7 6 5 4 3 2 1 0 name pms default 0 bit 0: performance monitoring update status (pms). this bit is set when the pms bits are set in all of the port functional blocks that are configured for port-level update control (i.e., all blocks that have pmum = 1). blocks that have pmum = 0 have no effect on this bit. in port-level software update mode, the port update request bit ( port.cr1 :pmu) should be held high until this status bit goes high. see section 8.7.4 . 0 = the associated update request signal is low or not all register updates are completed. 1 = the requested performance register updates are all completed. register name: port.srl register description: port status register latched register address: n * 80h + 1ah bit # 15 14 13 12 11 10 9 8 name tclkl bit # 7 6 5 4 3 2 1 0 name pmsl bit 8: transmit clock activity status latched (tclkl). this bit is set when the signal on the tclk pin used by this port (tclk n when tcc = 0, tclk1 when tcc = 1) is active. when set, this bit causes an interrupt if interrupt enables port.srie :tclkie, port.isrie :psrie, and global.isrie : pnisrie are all set. bit 0: performance monitoring update status latched (pmsl). this bit is set when the port.sr :pms status bit changes from low to high. when set, this bit causes an interrupt if interrupt enables port.srie :pmsie, port.isrie :psrie and global.isrie :pnisrie are all set. see section 8.7.4 . downloaded from: http:///
ds32506/ds32508/ds32512 69 of 130 register name: port.srie register description: port status register interrupt enable register address: n * 80h + 1ch bit # 15 14 13 12 11 10 9 8 name tclkie default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name pmsie default 0 0 0 0 0 0 0 0 bit 8: transmit clock activity latched status interrupt enable (tclkie). this bit is the interrupt enable for the port.srl :tclkl bit. 0 = mask the interrupt 1 = enable the interrupt bit 0: performance monitoring update latched status interrupt enable (pmsie). this bit is the interrupt enable for the port.srl :pmsl bit. 0 = mask the interrupt 1 = enable the interrupt downloaded from: http:///
ds32506/ds32508/ds32512 70 of 130 9.5 liu registers address offset register register description 20h liu.cr1 control register 1 22h liu.cr2 control register 2 24h liu.twscr1 transmit waveshaping control register 1 26h liu.twscr2 transmit waveshaping control register 2 28h liu.sr status register 2ah liu.srl status register latched 2ch liu.srie status register interrupt enable 2eh liu.rglr receive gain level register register name: liu.cr1 register description: liu control register 1 register address: n * 80h + 20h bit # 15 14 13 12 11 10 9 8 name jad[1:0] jas[1:0] default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name tlbo toe ttre tresadj[2:0] default 0 0 0 0 0 0 0 0 bits 11, 10: jitter attenuator depth (jad[1:0]). these bits select the jitter attenuator buffer depth. see section 8.4 . 00 = 16 bits 01 = 32 bits 10 = 64 bits 11 = 128 bits bit 9, 8: jitter attenuator select (jas[1:0]). these bits select the location of the jitter attenuator. see section 8.4 . 00 = disabled 01 = receive path 10 = transmit path 11 = transmit path bit 5: transmit liu lbo (tlbo). this bit is used to enable the transmit lbo circuit which causes the transmit signal to be preattenuated to mimic the attenuation of approx imately approximates about 225 feet of cable. this is used to reduce near-end crosstalk when the cable lengths are short. this signal is only valid in ds3 and sts-1 modes. see section 8.2.6 . 0 = disabled 1 = enabled bit 4: transmit output enable (toe). this bit enables the transmitter outputs (txp and txn). the transmitter continues to operate internally when the transmitter is tri-stated. only the line driver and driver monitor are disabled. see section 8.2.7 . note: this bit is ored with the associated toe input pin. 0 = txp and txn are high impedance 1 = txp and txn are driven bit 3: transmit termination resistor enable (ttre). this bit indicates when the transmitter internal termination is enabled. see section 8.2.8 . 0 = disabled, the transmitter is terminated externally 1 = enabled, the transmitter is terminated internally downloaded from: http:///
ds32506/ds32508/ds32512 71 of 130 bits 2, 0: transmit resistor adjustment (tresadj[2:0]). these bits are used to adjust the internal termination resistance of the transmitter. see section 8.2.8 . 000 = 75 001 = 82 010 = 90 011 = 100 100 = 68 101 = 62 110 = 56 111 = 50 register name: liu.cr2 register description: liu control register 2 register address: n * 80h + 22h bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name rfl2e rmon rtre rresadj[2:0] default 0 0 0 0 0 0 0 0 bit 5: receive fail 2 enable (rfl2e). this bit is used to enable the receive failure type 2 detection. see section 8.3.8 . 0 = disable receive failure type 2 detection 1 = enable receive failure type 2 detection bit 4: receive liu monitor mode (rmon). this bit is used to enable the receive liu monitor mode preamplifier. enabling the preamplifier adds about 14db of linear amplific ation for use in monitor applications where the signal has been reduced 20db using resistive attenuator circuits. note: when enabled, the preamp is turned on or off automatically depending upon the input signal level. see section 8.3.2 . 0 = disable the preamp 1 = enable the preamp bit 3: receive termination resistor enable (rtre). this bit indicates when the receiver internal termination is enabled. see section 8.3.1 . 0 = disabled, the receiver is terminated externally 1 = enabled, the receiver is terminated internally bits 2 to 0: receive resistor adjustment (rresadj[2:0]). these bits are used to adjust the internal termination resistance of the receiver. see section 8.3.1 . 000 = 75 001 = 82 010 = 90 011 = 100 100 = 68 101 = 62 110 = 56 111 = 50 downloaded from: http:///
ds32506/ds32508/ds32512 72 of 130 register name: liu.twscr1 register description: liu transmit waveshaping control register 1 register address: n * 80h + 24h bit # 15 14 13 12 11 10 9 8 name twsc[15:8] default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name twsc[7:0] default 0 0 0 0 0 0 0 0 see figure 8-1 , figure 8-2 , and figure 8-3 for illustrations of the first and second rise/fall time segments of the ds3 and sts-1 waveforms and the overshoot, one level, undershoot, and zero level segments for the e3 waveform. bits 15, 14: transmit waveshaping control (twsc[15:14]). in ds3 and sts-1 modes, this field adjusts the width of the first of two rising-edge segments. in e3 mode this field adjusts the width of the leading edge overshoot. ds3/sts-1 behavior e3 behavior 00 - normal first rise time normal overshoot width 01 - increase first rise time by 0.1ns increase overshoot width 10 - decrease first rise time by 0.1ns decrease overshoot width 11 - decrease first rise time by 0.2ns decrease overshoot width bits 13, 12: transmit waveshaping control (twsc[13:12]). in ds3 and sts-1 modes, this field adjusts the width of the second of two rising-edge segments. in e3 m ode this field adjusts the width of the pulse plateau. ds3/sts-1 behavior e3 behavior 00 - normal second rise time normal one level time 01 - increase second rise time by 0.1ns increase one level time by 0.15ns 10 - decrease second rise time by 0.1ns decrease one level time by 0.15ns 11 - decrease second rise time by 0.1ns decrease one level time by 0.3ns bits 11, 10: transmit waveshaping control (twsc[11:10]). in ds3 and sts-1 modes, this field adjusts the width of the first of two falling-edge segments. in e3 mode this field adjusts the width of the trailing edge undershoot. ds3/sts-1 behavior e3 behavior 00 - normal first fall time normal undershoot width 01 - increase first fall time by 0.1ns increase undershoot width by 0.15ns 10 - decrease first fall time by 0.1ns decrease undershoot width by 0.15ns 11 - decrease first fall time by 0.1ns decrease undershoot width by 0.3ns bits 9, 8: transmit waveshaping control (twsc[9:8]). in ds3 and sts-1 modes, this field adjusts the width of the second of two falling-edge segments. in e3 mode this fi eld adjusts the width of the zero after the trailing edge. ds3/sts-1 behavior e3 behavior 00 - normal second fall time normal zero level width 01 - increase second fall time by 0.1ns increase zero level width by 0.15ns 10 - decrease second fall time by 0.1ns decrease zero level width by 0.15ns 11 - decrease second fall time by 0.2ns decrease zero level width by 0.3ns bits 7, 6: transmit waveshaping control (twsc[7:6]). in ds3 and sts-1 modes, this field adjusts the amplitude of the first of two rising-edge segments. in e3 mode this field adjusts the amplitude of the leading edge overshoot. the 11 value is a special case in which the entire pulse is made narrower. ds3/sts-1 behavior e3 behavior 00 - normal first rise amplitude normal overshoot 01 - decrease first rise amplitude 15% decrease overshoot amplitude 2% 10 - increase first rise amplitude 15% increase overshoot amplitude 2% 11 - decrease pulse width by 0.15ns decrease pulse width by 0.15ns downloaded from: http:///
ds32506/ds32508/ds32512 73 of 130 bits 5, 4: transmit waveshaping control (twsc[5:4]). in ds3 and sts-1 modes, this field adjusts the amplitude of the second of two rising-edge segments. in e3 mode this field has no effect, except for the 11 value, which is a special case in which the entire pulse is made wider. ds3/sts-1 behavior e3 behavior 00 - normal rise amplitude normal pulse 01 - decrease second rise amplitude 15% normal pulse 10 - increase second rise amplitude 15% normal pulse 11 - increase pulse width by 0.15ns increase pulse width by 0.15ns bits 3, 2: transmit waveshaping control (twsc[3:2]). in ds3 and sts-1 modes, this field adjusts the amplitude of the first of two falling-edge segments. in e3 mode this field adjusts the amplitude of the trailing edge overshoot. the 11 value is a special case in which the entire pulse is made wider. ds3/sts-1 behavior e3 behavior 00 - normal first fall time normal undershoot 01 - decrease first fall time amplitude 15% decrease undershoot 2% 10 - increase first fall time amplitude 15% increase undershoot 2% 11 - increase pulse width by 0.15ns increase pulse width by 0.15ns bits 1, 0: transmit waveshaping control (twsc[1:0]). in ds3 and sts-1 modes, this field adjusts the fall time of the second of two falling-edge segments. in e3 mode this field has no effect, except for the 11 value, which is a special case in which the entire pulse is made narrower. ds3/sts-1 behavior e3 behavior 00 - normal second fall time normal pulse 01 - decrease second fall time amplitude 15% normal pulse 10 - increase second fall time amplitude 15% normal pulse 11 - decrease pulse width by 0.15ns decrease pulse width by 0.15ns downloaded from: http:///
ds32506/ds32508/ds32512 74 of 130 register name: liu.twscr2 register description: liu transmit waveshaping control register 2 register address: n * 80h + 26h bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name twsc[19:16] default 0 0 0 0 0 0 0 0 bits 3 to 0: transmit wavesh aping control (twsc[19:16]). this field adjusts overall amplitude of the transmit output pulse. 0000 - nominal amplitude (see table 11-6 and table 11-7 ) 0001 - increase amplitude by 3.75% 0010 - increase amplitude by 7.5% 0011 - increase amplitude by 11.25% 0100 - increase amplitude by 15% 0101 - increase amplitude by 20% 0110 - increase amplitude by 25% 0111 - increase amplitude by 30% 1000 - decrease amplitude by 12.5% 1001 - decrease amplitude by 9.375% 1010 - decrease amplitude by 6.25% 1011 - decrease amplitude by 3.125% 110x - increase amplitude to internal current limit 111x - increase amplitude to maximum, current limiting disabled downloaded from: http:///
ds32506/ds32508/ds32512 75 of 130 register name: liu.sr register description: liu status register register address: n * 80h + 28h bit # 15 14 13 12 11 10 9 8 name tdm tfail lomc default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name rpas rfail1 rfail2 rlol alos default 1 1 0 0 0 0 0 0 bit 10: transmit driver monitor (tdm). this bit indicates when the transmit driver is faulty. see section 8.2.9 . 0 = the transmit line driver is operating properly 1 = the transmit line driver is faulty bit 9: transmit output failure (tfail). this bit indicates when there is a failure on the transmit differential outputs (txp/txn). see section 8.2.9 . 0 = an open or short has not been detected on txp or txn 1 = an open or short has been detected on txp or txn bit 8: loss of master clock (lomc). this bit indicates whether or not the master reference clock (ds3, e3, or sts-1, depending on port.cr2 :lm[1:0] setting) is available from the clad block. see section 8.7.1 . 0 = the master reference clock is present 1 = that master reference clock is not present bit 4: receive preamp status (rpas). see section 8.3.2 . 0 = the receiver preamp is off 1 = the receiver preamp is on bit 3: receive failure type 1 (rfail1). see section 8.3.8 . 0 = a receive failure type 1 has not been detected on rxp or rxn 1 = a receive failure type 1 has been detected on rxp or rxn. bit 2: receive failure type 2 (rfail2). see section 8.3.8 . 0 = a receive failure type 2 has not been detected on rxp or rxn 1 = a receive failure type 2 has been detected on rxp or rxn. bit 1: receive loss of lock (rlol). see section 8.3.4 . 0 = the incoming clock frequency on rxp/rxn is within 7700ppm of the master reference clock 1 = the incoming clock frequency on rxp/rxn is more than 7900ppm away from the master reference clock bit 0: analog loss of signal (alos). see section 8.3.5 . 0 = an analog los (alos) condition has not been detected 1 = an alos condition has been detected downloaded from: http:///
ds32506/ds32508/ds32512 76 of 130 register name: liu.srl register description: liu status register latched register address: n * 80h + 2ah bit # 15 14 13 12 11 10 9 8 name jafl jael tdml tfaill lomcl default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name rglcl rpasl rfail1l rfail2l rloll alosl default 0 0 0 0 0 0 0 0 bit 12: jitter attenuator full latched (jafl). this bit is set when the jitter attenuator buffer is full, or when data has been lost due to a jitter attenuator buffer underflow or overflow. when set, this bit causes an interrupt if interrupt enables liu.srie :jafie, port.isrie :ldsrie and global.isrie :pnisrie are all set. see section 8.4 . bit 11: jitter attenuator empty latched (jael). this bit is set when the jitter attenuator buffer is empty, or when data has been lost due to a jitter attenuator buffer underflow or overflow. when set, this bit causes an interrupt if interrupt enables liu.srie :jaeie, port.isrie :ldsrie and global.isrie :pnisrie are all set. see section 8.4 . bit 10: transmit driver monitor change latched (tdml). this bit is set when the liu.sr :tdm bit changes state. when set, this bit causes an interrupt if interrupt enables liu.srie :tdmie, port.isrie :ldsrie and global.isrie :pnisrie are all set. bit 9: transmit output failure change latched (tfaill). this bit is set when the liu.sr :tfail bit changes state. when set, this bit causes an interrupt if interrupt enables liu.srie :tfailie, port.isrie :ldsrie and global.isrie :pnisrie are all set. bit 8: loss of master clock latched (lomcl). this bit is set when the liu.sr :lomc bit is set. when set, this bit causes an interrupt if interrupt enables liu.srie :lomcie, port.isrie :ldsrie and global.isrie :pnisrie are all set. bit 5: receive gain level change latched (rglcl). this bit is set when the receive gain level ( liu.rglr : rgl[7:0]) changes. when set, this bit causes an interrupt if interrupt enables liu.srie :rglcie, port.isrie :ldsrie and global.isrie :pnisrie are all set. bit 4: receive preamp status change latched (rpasl). this bit is set when the liu.sr :rpas bit changes state. when set, this bit causes an interrupt if interrupt enables liu.srie :rpasie, port.isrie :ldsrie and global.isrie :pnisrie are all set. bit 3: receive failure type 1 change latched (rfail1l). this bit is set when the liu.sr :rfail1 bit changes state. when set, this bit causes an interrupt if interrupt enables liu.srie :rfail1ie, port.isrie :ldsrie and global.isrie :pnisrie are all set. bit 2: receive failure type 2 change latched (rfail2l). this bit is set when the liu.sr :rfail2 bit changes state. when set, this bit causes an interrupt if interrupt enables liu.srie :rfail2ie, port.isrie :ldsrie and global.isrie :pnisrie are all set. bit 1: receive loss of lock change latched (rloll). this bit is set when the liu.sr :rlol bit changes state. when set, this bit causes an interrupt if interrupt enables liu.srie :rlolie, port.isrie :ldsrie and global.isrie :pnisrie are all set. bit 0: analog loss of signal change latched (alosl). this bit is set when the liu.sr :alos bit changes state. when set, this bit causes an interrupt if interrupt enables liu.srie :alosie, port.isrie :ldsrie and global.isrie :pnisrie are all set. downloaded from: http:///
ds32506/ds32508/ds32512 77 of 130 register name: liu.srie register description: liu status register interrupt enable register address: n * 80h + 2ch bit # 15 14 13 12 11 10 9 8 name jafie jaeie tdmie tfailie lomcie default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name rglcie rpasie rfail1ie rfail2ie rlolie alosie default 0 0 0 0 0 0 0 0 bit 12: jitter attenuator full interrupt enable (jafie). this bit is the interrupt enable for the liu.srl :jafl bit. 0 = interrupt disabled 1 = interrupt enabled bit 11: jitter attenuator empty interrupt enable (jaeie). this bit is the interrupt enable for the liu.srl :jael bit. 0 = interrupt disabled 1 = interrupt enabled bit 10: transmit driver monitor interrupt enable (tdmie). this bit is the interrupt enable for the liu.srl :tdml bit. 0 = interrupt disabled 1 = interrupt enabled bit 9: transmit output failure interrupt enable (tfailie). this bit is the interrupt enable for the liu.srl :tfaill bit. 0 = interrupt disabled 1 = interrupt enabled bit 8: loss of master clock interrupt enable (lomcie). this bit is the interrupt enable for the liu.srl :lomcl bit. 0 = interrupt disabled 1 = interrupt enabled bit 5: receive gain level change interrupt enable (rglcie). this bit is the interrupt enable for the liu.srl :rglcl bit. 0 = interrupt disabled 1 = interrupt enabled bit 4: receive preamp status interrupt enable (rpasie). this bit is the interrupt enable for the liu.srl :rpasl bit. 0 = interrupt disabled 1 = interrupt enabled bit 3: receive failure type 1 interrupt enable (rfail1ie). this bit is the interrupt enable for the liu.srl :rfail1l bit. 0 = interrupt disabled 1 = interrupt enabled bit 2: receive failure type 2 interrupt enable (rfail2ie). this bit is the interrupt enable for the liu.srl :rfail2l bit. 0 = interrupt disabled 1 = interrupt enabled bit 1: receive loss of lock interrupt enable (rlolie). this bit is the interrupt enable for the liu.srl :rloll bit. 0 = interrupt disabled 1 = interrupt enabled downloaded from: http:///
ds32506/ds32508/ds32512 78 of 130 bit 0: analog loss of signal interrupt enable (alosie). this bit is the interrupt enable for the liu.srl :alosl bit. 0 = interrupt disabled 1 = interrupt enabled register name: liu.rglr register description: liu receive gain level register register address: n * 80h + 2eh bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name rgl7 rgl6 rgl5 rgl4 rgl3 rgl2 rgl1 rgl0 default 0 0 0 0 0 0 0 0 bits 7 to 0: receive gain level (rgl[7:0]). this field reports the real-time receiver gain level in 0.25 db increments. values of 00C60h indicate receiver gain of 0db to +24db in 0.25db increments. values of f4Cfifth indicate receiver gain of -3db to -0.25db in 0.25db increments. see section 8.3.3 . downloaded from: http:///
ds32506/ds32508/ds32512 79 of 130 9.6 b3zs/hdb3 encoder registers address offset register register description 30h line.tcr b3zs/hdb3 transmit control register 32hC3eh unused register name: line.tcr register description: b3zs/hdb3 transmit control register register address: n * 80h + 30h bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name tzsd exzi bpvi tsei meims default 0 0 0 0 0 0 0 0 bit 4: transmit zero suppression encoding disable (tzsd) 0 = zero suppression (b3zs or hdb3) encoding is enabled 1 = zero suppression (b3zs or hdb3) encoding is disabled, and only ami encoding is performed bit 3: excessive zero insert enable (exzi). see section 8.2.3 . 0 = excessive zero event (exz) insertion is disabled 1 = excessive zero event insertion is enabled bit 2: bipolar violation insert enable (bpvi). see section 8.2.3 . 0 = bipolar violation (bpv) insertion is disabled 1 = bipolar violation insertion is enabled. bit 1: transmit single error insert (tsei). when line.tcr :meims = 0, this bit is used to insert errors of the type(s) specified by exzi and bpvi in the transmit data stream . a zero-to-one transition caus es a single error to be inserted. for a second error to be inserted, this bit must be set to 0, and then back to 1. note: if line.tcr :meims is low, and this bit transitions more than once between error insertion opportunities, only one error is inserted. see section 8.7.5 . bit 0: manual error insert mode select (meims). this bit specifies the source of the error insertion signal for the transmit encoder/decoder block. note: if the tmei pin or t sei bit is one, changing the state of this bit may cause an error to be inserted. see section 8.7.5 . 0 = block-level error insertion using the line.tcr :tsei control bit 1 = port-level or global-level error insertion as specified by port.cr1 :meims downloaded from: http:///
ds32506/ds32508/ds32512 80 of 130 9.7 b3zs/hdb3 decoder registers address offset register register description 40h line.rcr b3zs/hdb3 receive control register 42h unused 44h line.rsr b3zs/hdb3 receive status register 46h line.rsrl b3zs/hdb3 receive status register latched 48h line.rsrie b3zs/hdb3 receive status r egister interrupt enable 4ah unused 4ch line.rbpvcr b3zs/hdb3 receive bipolar violation count register 4eh line.rexzcr b3zs/hdb3 receive excessive zero count register register name: line.rcr register description: b3zs/hdb3 receive control register register address: n * 80h + 40h bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name e3cve rezsf rdzsf rzsd default 0 0 0 0 0 0 0 0 bit 3: e3 code violation enable (e3cve). in e3 mode ( port.cr2 :lm[1:0] = 01), this bit specifies whether the line.rbpvcr register counts bipolar violations or e3 coding violations. note: e3 line coding violations are defined in itu o.161 as consecutive bipolar violations of the same polarity. this bit is ignored in b3zs mode. see section 8.3.6.2 . 0 = bipolar violations. 1 = e3 line coding violations bit 2: receive bpv error detection zero suppression code format (rezsf). when rezsf = 0, bpv error detection detects a b3zs signature if a zero is follow ed by a bipolar violation (bpv) , and an hdb3 signature if two zeros are followed by a bpv. when rezsf = 1, bpv error detection detects a b3zs signature if a zero is followed by a bpv that has the opposite polarity of the bpv in the previous b3zs signature, and an hdb3 signature if two zeros are followed by a bpv that ha s the opposite polarity of the bpv in the previous hdb3 signature. note: immediately after a reset (rst or dprst bit high), this bit is ignored. the first b3zs signature is defined as a zero followed by a bpv, and the first hdb3 signature is defi ned as two zeros followed by a bpv. all subsequent b3zs/hdb3 signatures are determined by the setting of this bit. note: the default setting (rezsf = 0) conforms to itu o.162. the default setting may falsel y ignore actual bpvs that are not codewords. it is recommended that rezsf be set to one for most applications. this setti ng is more robust to accurately detect codewords. see section 8.3.6.2 . bit 1: receive zero suppression decoding zero suppression code format (rdzsf). when rdzsf = 0, zero suppression decoding detects a b3zs signature if a zero is followed by a bipolar violation (bpv), and an hdb3 signature if two zeros are followed by a bpv. when rd zsf = 1, zero suppression decoding detects a b3zs signature if a zero is followed by a bpv that has the opposi te polarity of the bpv in the previous b3zs signature, and an hdb3 signature if two zeros are followed by a bpv t hat has the opposite polarity of the bpv in the previous hdb3 signature. note: immediately after a reset (rst or dprst bit high), this bit is ignored. the first b3zs signature is defined as a zero followed by a bpv, and the first hdb3 signature is defined as two zeros followed by a bpv. all subsequent b3zs/hdb3 signatures are determined by the setting of this bit. note: the default setting (rdzsf = 0) may falsely decode actual bpvs that are not codewords. it is recomm ended that rdzsf be set to one for most applications. this setting is more robust to accurately detect codewords. see section 8.3.6.2 . bit 0: receive zero suppression decoding disable (rzsd) 0 = zero suppression (b3zs or hdb3) decoding is enabled 1 = zero suppression (b3zs or hdb3) decoding is disabled, and only ami decoding is performed downloaded from: http:///
ds32506/ds32508/ds32512 81 of 130 register name: line.rsr register description: b3zs/hdb3 receive status register register address: n * 80h + 44h bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name exzc bpvc los default 0 0 0 0 0 0 0 0 bit 3: excessive zero count (exzc). see section 8.3.6 . 0 = the receive excessive zero count register ( line.rexzcr ) is zero 1 = the receive excessive zero count register ( line.rexzcr ) is one or more bit 1: bipolar violation count (bpvc). see section 8.3.6 . 0 = the receive bipolar violation count register ( line.rbpvcr ) is zero 1 = the receive bipolar violation count register ( line.rbpvcr ) is one or more bit 0: loss of signal (los). see section 8.3.5. 0 = receive line interface is not in a los condition 1 = receive line interface is in an los condition register name: line.rsrl register description: b3zs/hdb3 receive status register latched register address: n * 80h + 46h bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name zscdl exzl exzcl bpvl bpvcl losl default 0 0 0 0 0 0 0 0 bit 5: zero suppression code detect latched (zscdl). this bit is set when a b3zs or hdb3 signature is detected. when set, this bit causes an interrupt if interrupt enables line.rsrie :zscdie, port.isrie :ldsrie and global.isrie :pnisrie are all set. see section 8.3.6 . bit 4: excessive zero latched (exzl). this bit is set when an excessive zero event is detected on the incoming bipolar data stream. when set, this bit causes an interrupt if interrupt enables line.rsrie :exzie, port.isrie :ldsrie and global.isrie :pnisrie are all set. see section 8.3.6 . bit 3: excessive zero count latched (exzcl). this bit is set when line.rsr :exzc transitions from zero to one. when set, this bit causes an interrupt if interrupt enables line.rsrie :exzcie, port.isrie :ldsrie and global.isrie :pnisrie are all set. see section 8.3.6 . bit 2: bipolar violation latched (bpvl). this bit is set when a bipolar violation (or e3 lcv if enabled) is detected on the incoming bipolar data stream. when set, this bit causes an interrupt if interrupt enables line.rsrie :bpvie, port.isrie :ldsrie and global.isrie :pnisrie are all set. see section 8.3.6 . bit 1: bipolar violation count latched (bpvcl). this bit is set when line.rsr :bpvc transitions from zero to one. when set, this bit causes an interrupt if interrupt enables line.rsrie :bpvcie, port.isrie :ldsrie and global.isrie :pnisrie are all set. see section 8.3.6 . bit 0: loss of signal change latched (losl). this bit is set when line.rsr :los changes state. when set, this bit causes an interrupt if interrupt enables line.rsrie :losie, port.isrie :ldsrie and global.isrie :pnisrie are all set. see section 8.3.5. downloaded from: http:///
ds32506/ds32508/ds32512 82 of 130 register name: line.rsrie register description: b3zs/hdb3 receive status register interrupt enable register address: n * 80h + 48h bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name zscdie exzie exzcie bpvie bpvcie losie default 0 0 0 0 0 0 0 0 bit 5: zero suppression code detect interrupt enable (zscdie). this bit is the interrupt enable for the line.rsrl :zscdl status bit. 0 = mask the interrupt 1 = enable the interrupt bit 4: excessive zero interrupt enable (exzie). this bit is the interrupt enable for the line.rsrl :exzl status bit. 0 = mask the interrupt 1 = enable the interrupt bit 3: excessive zero count interrupt enable (exzcie). this bit is the interrupt enable for the line.rsrl :exzcl status bit. 0 = mask the interrupt 1 = enable the interrupt bit 2: bipolar violation interrupt enable (bpvie). this bit is the interrupt enable for the line.rsrl :bpvl status bit. 0 = mask the interrupt 1 = enable the interrupt bit 1: bipolar violation count interrupt enable (bpvcie). this bit is the interrupt enable for the line.rsrl :bpvcl status bit. 0 = mask the interrupt 1 = enable the interrupt bit 0: loss-of-signal inte rrupt enable (losie). this bit is the interrupt enable for the line.rsrl :losl status bit. 0 = mask the interrupt 1 = enable the interrupt downloaded from: http:///
ds32506/ds32508/ds32512 83 of 130 register name: line.rbpvcr register description: b3zs/hdb3 receive bipolar violation count register register address: n * 80h + 4ch bit # 15 14 13 12 11 10 9 8 name bpv[15:8] default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name bpv[7:0] default 0 0 0 0 0 0 0 0 bits 15 to 0: bipolar vi olation count (bpv[15:0]). these 16 bits indicate the number of bipolar violations detected on the incoming bipolar data stream. see section 8.3.6 . register name: line.rexzcr register description: b3zs/hdb3 receive excessive zero count register register address: n * 80h + 4eh bit # 15 14 13 12 11 10 9 8 name exz[15:8] default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name exz[7:0] default 0 0 0 0 0 0 0 0 bit 15 to 0: excessive ze ro count (exz[15:0]). these 16 bits indicate the number of excessive zero conditions detected on the incoming bipolar data stream. see section 8.3.6 . downloaded from: http:///
ds32506/ds32508/ds32512 84 of 130 9.8 bert registers address offset register register description 50h bert.cr bert control register 52h bert.pcr bert pattern configuration register 54h bert.spr1 bert seed/pattern register 1 56h bert.spr2 bert seed/pattern register 2 58h bert.teicr transmit error insertion control register 5ah unused 5ch bert.sr bert status register 5eh bert.srl bert status register latched 60h bert.srie bert status register interrupt enable 62h unused 64h bert.rbecr1 receive bit error count register 1 66h bert.rbecr2 receive bit error count register 2 68h bert.rbcr1 receive bit count register 1 6ah bert.rbcr2 receive bit count register 2 6ch unused 6eh unused register name: bert.cr register description: bert control register register address: n * 80h + 50h bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name pmum lpmu rnpl rpic mpr aprd tnpl tpic default 0 0 0 0 0 0 0 0 bit 7: performance monitoring update mode (pmum). this bit specifies the source of the performance monitoring update signal for the bert block. see section 8.7.4 . note: if rpmu or lpmu is one, changing the state of this bit may cause a performance monitoring update to occur. 0 = block-level update via bert.cr :lpmu 1 = port-level or global update as specified by port.cr1 :pmum bit 6: local performance monitoring update (lpmu). when bert.cr :pmum = 0, this bit updates the performance monitoring registers in the bert block. when this bit transitions from low to high, the bert.rbecr and bert.rbcr registers are updated with the latest counter values and the counters are reset. this bit should remain high until the performance monitor update status bit ( bert.sr :pms) goes high, and then it should be brought back low, which clears the pms status bit. if a counter increment occurs at the exact same time as the counter reset, the counter is loaded with a value of one, and the counter is non-zero latched status bit is set. see section 8.7.4 . bit 5: receive new pattern load (rnpl). a zero-to-one transition of this bit causes the programmed test pattern (qrss, pts, plf[4:0], ptf[4:0] in the bert.pcr register, and bsp[31:0] in the bert.spr registers) to be loaded into the receive pattern generator. this bit must be changed to zero and back to one for another pattern to be loaded. loading a new pattern forces the receive patte rn generator out of the sync state which causes a resynchronization to be initiated. note: the test pattern fields mentioned above must not change for four rclk cycles after this bit transitions from zero to one. see section 8.5.1 . downloaded from: http:///
ds32506/ds32508/ds32512 85 of 130 bit 4: receive pattern inversion control (rpic) . see section 8.5.1 . 0 = do not invert the incoming data stream 1 = invert the incoming data stream bit 3: manual pattern resynchronization (mpr). a zero-to-one transition of this bit causes the receive pattern generator to resynchronize to the incoming pattern. this bit must be changed to zero and back to one for another resynchronization to be initiated. note: a manual resynchroni zation forces the pattern detector out of the sync state. see section 8.5.2 . bit 2: automatic pattern resynchronization disable (aprd). when aprd = 0, the receive pattern generator automatically resynchronizes to the incoming pattern if six or more times during the current 64-bit window the incoming data stream bit and the receive pattern generator output bit did not match. when aprd = 1, the receive pattern generator does not automatically resynchronize to the incoming pattern. note: automatic synchronization is prevented by not allowing the receive pattern generator to automatically exit the s ync state. see section 8.5.2 . bit 1: transmit new pattern load (tnpl). a zero-to-one transition of this bit causes the programmed test pattern (qrss, pts, plf[4:0], ptf[4:0] in the bert.pcr register, and bsp[31:0] in the bert.spr registers) to be loaded into the transmit pattern generator. this bit must be changed to zero and back to one for another pattern to be loaded. note: the test pattern fields mentioned above must not change for four tclk cycles after this bit transitions from zero to one. see section 8.5.1 . bit 0: transmit pattern inversion control (tpic). see section 8.5.1 . 0 = do not invert the outgoing data stream 1 = invert the outgoing data stream register name: bert.pcr register description: bert pattern configuration register register address: n * 80h + 52h bit # 15 14 13 12 11 10 9 8 name ptf[4:0] default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name qrss pts plf[4:0] default 0 0 0 0 0 0 0 0 bits 12 to 8: pattern tap feedback (ptf[4:0]). these five bits control the prbs tap feedback of the pattern generator. the tap feedback is from bit y of the pattern generator (y = ptf[4:0] + 1). these bits are ignored when the bert block is programmed for a repetitive pattern (p ts = 1). for a prbs signal, the feedback is an xor of bit n and bit y. see section 8.5.1 . bit 6: qrss enable (qrss). see section 8.5.1 . 0 = disabled: the pattern generator configurati on is controlled by pts, plf[4:0], ptf[4:0], and bsp[31:0] 1 = enabled: the pattern generator configuration is forced to a prbs pattern with a generating polynomial of x 20 + x 17 + 1, and the output of the pattern generator is forced to one if the next 14 output bits are all zero. bit 5: pattern type select (pts). see section 8.5.1 . 0 = prbs pattern 1 = repetitive pattern. bits 4 to 0: pattern length feedback (plf[4:0]). this field controls the length feedback of the pattern generator. the length feedback is from bit n of the pattern generator (n = plf[4:0] + 1). for a prbs signal, the feedback is an xor of bit n and bit y. for a repetitive pattern the feedback is bit n. see section 8.5.1 . downloaded from: http:///
ds32506/ds32508/ds32512 86 of 130 register name: bert.spr1 register description: bert seed/pattern register #1 register address: n * 80h + 54h bit # 15 14 13 12 11 10 9 8 name bsp[15:8] default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name bsp[7:0] default 0 0 0 0 0 0 0 0 bits 15 to 0: bert seed/pattern (bsp[15:0]) register name: bert.spr2 register description: bert seed/pattern register #2 register address: n * 80h + 56h bit # 15 14 13 12 11 10 9 8 name bsp[31:24] default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name bsp[23:16] default 0 0 0 0 0 0 0 0 bits 15 to 0: bert seed/pattern (bsp[31:16]) bert seed/pattern (bsp[31:0]). this 32-bit field is the programmable seed for a transmit prbs pattern, or the programmable pattern for a transmit or receive repetitive pattern. bsp[31] is the first bit output on the transmit side for a 32-bit repetitive pattern or 32-bit prbs. bsp[31] is t he first bit input on the receive side for a 32-bit repetitive pattern. see section 8.5.1 . downloaded from: http:///
ds32506/ds32508/ds32512 87 of 130 register name: bert.teicr register description: bert transmit error insertion control register register address: n * 80h + 58h bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name teir[2:0] bei tsei meims default 0 0 0 0 0 0 0 0 bits 5 to 3: transmit error insertion rate (teir[2:0]). this field indicates the rate at which errors are automatically inserted in the output data stream. one out of every 10 n bits is inverted, where n = teir[2:0]. a value of 0 disables error insertion. a value of 1 results in every 10th bit being inverted. a value of 2 result in every 100th bit being inverted. error insertion starts when this field is written with a non-zero value. if this field is written during an error insertion, the new error rate is used after the next error is inserted. see section 8.5.3.1 . bit 2: bit error insertion enable (bei). see section 8.5.3.1 . 0 = single-bit error insertion is disabled 1 = single-bit error insertion is enabled bit 1: transmit single error insert (tsei). when bert.teicr :meims = 0 and bei = 1, this bit is used to insert single-bit errors in the outgoing bert data stream. a zero-to-one transition causes a single bit error to be inserted. for a second bit error to be inserted, this bit must be set to 0, and back to 1. note: if meims is low, and this bit transitions more than once between error insertion op portunities, only one error is inserted. see section 8.7.5. bit 0: manual error insert mode select (meims). this bit specifies the source of the error insertion signal for the bert block. note: if tmei or tsei is one, changing the st ate of this bit may cause a bit error to be inserted. see section 8.7.5 . 0 = error insertion is initiated by the bert.teicr :tsei register bit 1 = error insertion is initiated by the transmit manual error insertion signal (tmei) specified by the port.cr1 :meims register bit. downloaded from: http:///
ds32506/ds32508/ds32512 88 of 130 register name: bert.sr register description: bert status register register address: n * 80h + 5ch bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name pms bec oos default 0 0 0 0 1 0 0 0 bit 3: performance monitoring update status (pms). this bit is set when the performance monitoring registers ( bert.rbcr and bert.rbecr ) have been updated. pms is asynchronously forced low when the bert.cr :lpmu bit ( bert.cr :pmum = 0) or rpmu signal ( bert.cr :pmum = 1) goes low. see section 8.7.4 . 0 = the associated update request signal is low or not all register updates are completed 1 = the requested performance register updates are all completed bit 1: bit error count (bec). see section 8.5.1 . 0 = the bit error count is zero 1 = the bit error count is one or more bit 0: out of synchronization (oos). see section 8.5.1 . 0 = the receive pattern generator is synchronized to the incoming pattern 1 = the receive pattern generator is not synchronized to the incoming pattern register name: bert.srl register description: bert status register latched register address: n * 80h + 5eh bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name pmsl bel becl oosl default 0 0 0 0 0 0 0 0 bit 3: performance monitoring update status latched (pmsl). this bit is set when the bert.sr :pms bit transitions from zero to one. when set, this bit causes an interrupt if interrupt enables bert.srie :pmsie, port.isrie :bsrie and global.isrie :pnisrie are all set. bit 2: bit error latched (bel). this bit is set when a bit error is detected in the received pattern. when set, this bit causes an interrupt if interrupt enables bert.srie :beie, port.isrie :bsrie and global.isrie :pnisrie are all set. bit 1: bit error count latched (becl). this bit is set when the bert.sr :bec bit transitions from zero to one. when set, this bit causes an interrupt if interrupt enables bert.srie :becie, port.isrie :bsrie and global.isrie :pnisrie are all set. bit 0: out of synchronization latched (oosl). this bit is set when the bert.sr :oos bit changes state. when set, this bit causes an interrupt if interrupt enables bert.srie :oosie, port.isrie :bsrie and global.isrie :pnisrie are all set. downloaded from: http:///
ds32506/ds32508/ds32512 89 of 130 register name: bert.srie register description: bert status register interrupt enable register address: n * 80h + 60h bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name pmsie beie becie oosie default 0 0 0 0 0 0 0 0 bit 3: performance monitoring update status interrupt enable (pmsie). this bit is the interrupt enable for the bert.srl :pmsl status bit. 0 = mask the interrupt 1 = enable the interrupt bit 2: bit error interrupt enable (beie). this bit is the interrupt enable for the bert.srl :bel status bit. 0 = mask the interrupt 1 = enable the interrupt bit 1: bit error count interrupt enable (becie). this bit is the interrupt enable for the bert.srl :becl status bit. 0 = mask the interrupt 1 = enable the interrupt bit 0: out of synchronization interrupt enable (oosie). this bit is the interrupt enable for the bert.srl :oosl status bit. 0 = mask the interrupt 1 = enable the interrupt register name: bert.rbecr1 register description: bert receive bit error count register #1 register address: n * 80h + 64h bit # 15 14 13 12 11 10 9 8 name bec[15:8] default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name bec[7:0] default 0 0 0 0 0 0 0 0 bits 15 to 0: bit error count (bec[15:0]) downloaded from: http:///
ds32506/ds32508/ds32512 90 of 130 register name: bert.rbecr2 register description: bert receive bit error count register #2 register address: n * 80h + 66h bit # 15 14 13 12 11 10 9 8 name default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name bec[23:16] default 0 0 0 0 0 0 0 0 bits 7 to 0: bit error count (bec[23:16]) bit error count (bec[23:0]). this field is the holding register for an internal bert bit error counter that tracks the number of bit errors detected in the incoming data stream since the last performance monitoring update. the internal counter stops incrementing when it reaches a count of ff ffffh and does not increment when an oos condition exists. this register is updated when a pe rformance monitoring update is performed. see section 8.7.4 . the source for the performance monitoring update signal is specified by the bert.cr :pmum bit. register name: bert.rbcr1 register description: bert receive bit count register #1 register address: n * 80h + 68h bit # 15 14 13 12 11 10 9 8 name bc[15:8] default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name bc[7:0] default 0 0 0 0 0 0 0 0 bits 15 to 0: bit count (bc[15:0]) register name: bert.rbcr2 register description: bert receive bit count register #2 register address: n * 80h + 6ah bit # 15 14 13 12 11 10 9 8 name bc[31:24] default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name bc[23:16] default 0 0 0 0 0 0 0 0 bits 15 to 0: bit count (bc[31:16]) bit count (bc[31:0]). this field is the holding register for an internal bert bit counter that tracks the total number of bit received in the incoming data stream since the last performance monitoring update. the internal counter stops incrementing when it reaches a count of ffff ffffh and does not increment when an oos condition exists. this register is updated when a performance monitoring update is performed. see section 8.7.4 . the source for the performance monitoring update signal is specified by the bert.cr :pmum bit. downloaded from: http:///
ds32506/ds32508/ds32512 91 of 130 10. jtag information the ds325xx lius support the standard inst ruction codes sample/preload, bypass, and extest. optional public instructions included are highz, clamp, and id code. the devices contain the following items, which meet the requirements set by the ieee 1149.1 standar d test access port and boundary scan architecture: test access port (tap) tap controller instruction register bypass register boundary scan register device identification register the tap has the necessary interface pins, namely jtclk , jtrst , jtdi , jtdo , and jtms . details on these pins can be found in table 7-9 . details about the boundary scan architecture and the tap can be found in ieee 1149.1- 1990, ieee 1149.1a-1993, and ieee 1149.1b-1994. ieee 1149.1 requires a minimum of two te st registersthe bypass register and the bound ary scan register. the bypass register is a 1-bit shift regi ster used with the bypass, clamp, and hi ghz instructions to provide a short path between jtdi and jtdo. the boundary scan register contains a shift register path and a latched parallel output for control cells and digital i/o cells. ds325xx bsdl files are available at www.maxim-ic.com/techs upport/telecom/bsdl.htm. an optional test register, the identification register, has also been included in the device design. the identification register contains a 32-bit shift register and a 32-bit latched parallel output. table 10-1 shows the identification register c ontents for the ds32506, ds32508, and ds32512 devices. table 10-1. jtag id code part revision device code manufacturer code required ds32506 consult factory 0000 0000 0111 1000 00010100001 1 ds32508 consult factory 0000 0000 0111 1001 00010100001 1 ds32512 consult factory 0000 0000 0111 1010 00010100001 1 downloaded from: http:///
ds32506/ds32508/ds32512 92 of 130 11. electrical characteristics absolute maximum ratings voltage range on any input or output lead with respect to v ss -0.3v to +5.5v supply voltage range with respect to v ss vdd33...-0.3v to +3.63v vdd18 ..-0.1v to +1.89v ambient operating temperature range* ....-40c to +85c junction operating temperature range -40c to +125c storage temperature range ...-55c to +125c soldering temperature.s ee ipc/jedec j-std-020 specification stresses beyond those listed under absolute maximum ratings may c ause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to the absolute ma ximum rating conditions fo r extended periods may affect device reliability. *ambient operating temperature range when device is mounted on a four-layer jedec test board with no airflow. note: the typical values listed in the following tables and operation at -40 o c are not production test ed, but are guaranteed by design (gbd). table 11-1. recommended dc operating conditions (t a = -40c to +85c) parameter symbol conditions min typ max units vdd18 1.71 1.8 1.89 digital supply voltage vdd33 3.135 3.300 3.465 v analog supply voltage avdd cvdd, jvdd, rvdd, and tvdd 1.71 1.80 1.89 v logic 1, all other input pins v ih 2.0 3.6 v logic 0, all other input pins v il -0.3 +0.8 v downloaded from: http:///
ds32506/ds32508/ds32512 93 of 130 table 11-2. dc characteristics (vdd18 = 1.8v 5%, vdd33 = 3.3v 5%, avdd = 1.8v 5%, t a = -40c to +85c.) parameter symbol conditions min typ max units ds32506 248 320 ds32508 324 420 supply current, vdd18 (note 1) i dd18 ds32512 476 620 ma ds32506 90 165 ds32508 120 220 supply current, vdd33 (note 1) i dd33 ds32512 180 330 ma ds32506 170 200 ds32508 220 260 supply current, transmitters disabled (all toe = 0), vdd18 (note 2) i ddtts18 ds32512 320 380 ma ds32506 90 165 ds32508 120 220 supply current, transmitters disabled (all toe = 0), vdd33 (note 2) i ddtts33 ds32512 180 330 ma supply current, power-down (all tpd = rpd = 1), vdd18 (notes 2, 3) i ddpd18 ds32506, ds32508, ds32512 16 40 ma supply current, power-down (all tpd = rpd = 1), vdd33 (notes 2, 3) i ddpd33 ds32506, ds32508, ds32512 5.3 10 ma lead capacitance c io 7 10 pf input leakage, input pins with pullup i il (note 4) -300 +10 a input leakage, all other input pins i il (note 4) -50 +10 a output leakage (when high-z) i lo (note 4) -10 +10 a output voltage (i o = -4.0ma) v oh 2.4 vdd33 v output voltage (i o = +4.0ma) v ol 0 0.4 v note 1: tclkn = clkc = 51.84mhz; lmn[1:0] = 10 (sts-1 mode); txpn/txnn driving all ones into 75 resistive loads; analog loopback enabled; all other inputs at vdd33 or grounded; all other outputs open. note 2: tclkn = clkc = 51.84mhz; lmn[1:0] = 10 (sts-1 mode); other in puts at vdd33 or grounded; digital outputs left open circuited. note 3: hw = 0, clad[6:0] = 0000000 (disabled), g1srs[3:0] = 0000 (disable), cs = 1 (inactive). note 4: 0v < v in < vdd18 for all other digital inputs. downloaded from: http:///
ds32506/ds32508/ds32512 94 of 130 table 11-3. framer interface timing (vdd18 = 1.8v 5%, vdd33 = 3.3v 5%, avdd = 1.8v 5%, t a = -40c to +85c.) (see figure 11-1 and figure 11-2 .) parameter symbol conditions min typ max units (notes 1, 2) 22.4 (notes 2, 3) 29.1 rclk/tclk clock period t1 (notes 2, 4) 19.3 ns rclk duty cycle t2/t, t3/t1 (notes 5, 6) 45 50 55 % tclk duty cycle t2/t, t3/t1 (note 6) 30 70 % liu reference clock duty cycle t2 /t, t3/t1 (notes 6, 7) 30 70 % tpos/tdat, tneg to tclk setup time t4 (notes 6, 8) 3 ns tpos/tdat, tneg hold time t5 (notes 6, 8) 1 ns rclk to rpos/rdat, rneg/rlcv value change t6 (notes 5, 6, 9) 1 7 ns rclk rise and fall time t7 (notes 6, 10 ) 1 2 ns tclk rise and fall time t8 (notes 5, 11) 2 ns note 1: ds3 mode. note 2: 78mhz is the maximum instantaneous frequency for a gapped clo ck. the maximum average frequency is 45.094mhz for ds3, 34.643mhz for e3, and 52.255mhz for sts-1. note 3: e3 mode. note 4: sts-1 mode. note 5: outputs loaded with 25pf, measured at 50% threshold. note 6: not tested during production test. note 7: the liu reference clock must be a 20ppm low-jitter clock. see section 8.7.1 for more information on reference clocks. note 8: when tclki = 0, tpos/tdat and tneg are sampled on the rising edge of tclk. when tclki = 1, tpos/tdat and tneg are sampled on the falling edge of tclk. note 9: when rclki = 0, rpos/rdat and rneg/rlcv are updated on the falling edge of rclk. when rclki = 1, rpos/rdat and rneg/rlcv are updated on the rising edge of rclk. note 10: outputs loaded with 25pf, measured between v ol(max) and v oh(min) . note 11: measured between v il(max) and v ih(min) . downloaded from: http:///
ds32506/ds32508/ds32512 95 of 130 figure 11-1. transmitter fram er interface timing diagram tclk (inverted) tpos/tdat tneg t4 t5 t1 t2 t3 tclk (normal) t 8 figure 11-2. receiver framer interface timing diagram rclk (normal) rpos/rdat rneg/rlcv t6 t1 t2 t3 rclk (inverted) t7 downloaded from: http:///
ds32506/ds32508/ds32512 96 of 130 table 11-4. receiver input char acteristicsds3 and sts-1 modes (vdd18 = 1.8v 5%, vdd33 = 3.3v 5%, avdd = 1.8v 5%, t a = -40c to +85c.) parameter min typ max units receive sensitivity (length of cable) 1500 ft signal-to-noise ratio, interfering signal test (notes 1, 2) 10 input pulse amplitude, rmon = 0 (notes 2, 3) 1000 mvpk input pulse amplitude, rmon = 1 (note 2, 3) 200 mvpk analog los declare, rmon = 0 (note 4) -23 -25 db analog los clear, rmon = 0 (note 4) -20 -22 db analog los declare, rmon = 1 (note 4) -37 -39 db analog los clear, rmon = 1 (note 4) -34 -36 db intrinsic jitter generation (note 2) 0.02 ui p-p note 1: an interfering signal (2 15 - 1 prbs, b3zs encoded, compliant waveshape, nominal bit rate) is added to the input signal. the combined signal is passed through 0 to 900 feet of coaxial cable and presented to the ds325xx receiver. this spec indicates the lowest s ignal- to-noise ratio that results in a bit error ratio 10 -9 . note 2: not tested during production test. note 3: measured on the line side (i.e., the bnc connector side) of the 1:1 receive transformer (see figure 4-1 ). during measurement, incoming data traffic is unframed 2 15 - 1 prbs. note 4: with respect to nominal 800mvpk signal. table 11-5. receiver input characteristicse3 mode (vdd18 = 1.8v 5%, vdd33 = 3.3v 5%, avdd = 1.8v 5%, t a = -40c to +85c.) parameter min typ max units receive sensitivity (length of cable) 900 1200 1500 ft signal-to-noise ratio, interfering signal test (notes 1, 2) 12 input pulse amplitude, rmon = 0 (notes 2, 3) 1300 mvpk input pulse amplitude, rmon = 1 (notes 2, 3) 260 mvpk analog los declare, rmon = 0 (note 4) -24 db analog los clear, rmon = 0 (note 4) -18 db analog los declare, rmon = 1 (note 4) -44 db analog los clear, rmon = 1 (note 4) -38 db intrinsic jitter generation (note 2) 0.03 ui p-p note 1: an interfering signal (2 23 - 1 prbs, hdb3 encoded, compliant waveshape, nominal bit rate) is added to the input signal. the combined signal is passed through 0 to 900 feet of coaxial cable and presented to the ds325xx receiver. this spec indicates the lowest signal-to-noise ratio that results in a bit error ratio 10 -9 . note 2: not tested during production test. note 3: measured on the line side (i.e., the bnc connector side) of the 1:1 receive transformer (see figure 4-1). during measurement, incoming data traffic is unframed 2 23 - 1 prbs. note 4: with respect to nominal 1000mvpk signal. downloaded from: http:///
ds32506/ds32508/ds32512 97 of 130 table 11-6. transmitter output ch aracteristicsds3 and sts-1 modes (vdd18 = 1.8v 5%, vdd33 = 3.3v 5%, avdd = 1.8v 5%, t a = -40c to +85c.) parameter min typ max units ds3 output pulse amplitude, tlbo = 0 (note 1) 700 800 900 mvpk ds3 output pulse amplitude, tlbo = 1 (note 1) 500 600 700 mvpk sts-1 output pulse amplitude, tlbo = 0 (note 1) 700 800 900 mvpk sts-1 output pulse amplitude, tlbo = 1 (note 1) 500 600 700 mvpk ratio of positive and negative pulse-peak amplitudes 0.9 1.0 1.1 ds3 power level at 22.368mhz (note 2) -1.8 +5.7 dbm ds3 power level at 44.736mhz vs. power level at 22.368mhz (note 2) -20 db transmit driver monitor minimum threshold (v txmin ), tlbo = 0 680 mvpk transmit driver monitor minimum threshold (v txmin ), tlbo = 1 480 mvpk transmit driver monitor maximum threshold (v txmax ), tlbo = 0 920 mvpk transmit driver monitor maximum threshold (v txmax ), tlbo = 1 720 mvpk note 1: measured on the line side (i.e., the bnc connecto r side) of the 1:1 transmit transformer ( figure 4-1 ). note 2: unframed all-ones output signal, 3khz bandwidth. table 11-7. transmitter out put characteristicse3 mode (vdd18 = 1.8v 5%, vdd33 = 3.3v 5%, avdd = 1.8v 5%, t a = -40c to +85c.) parameter min typ max units output pulse amplitude (note 1) 900 1000 1100 mvpk pulse width (note 1) 14.55 ns positive/negative pulse amplitude ratio (at centers of pulses) (note 1) 0.95 1.00 1.05 positive/negative pulse width ratio (at nominal half amplitude) 0.95 1.00 1.05 transmit driver monitor minimum threshold (v txmin ) 880 mvpk transmit driver monitor maximum threshold (v txmax ) 1120 mvpk note 1: measured on the line side (i.e., the bnc connecto r side) of the 1:1 transmit transformer ( figure 4-1 ). downloaded from: http:///
ds32506/ds32508/ds32512 98 of 130 table 11-8. parallel cpu interface timing (vdd18 = 1.8v 5%, vdd33 = 3.3v 5%, avdd = 1.8v 5%, t a = -40c to +85c.) (see figure 11-3 , figure 11-4 , figure 11-5 , figure 11-6 , figure 11-7 , figure 11-8 , figure 11-9 , and figure 11-10 .) parameter symbol min typ max units setup time for a[10:0] valid to rd , wr , or ds active (notes 1, 2) t1 0 ns setup time for cs active to rd , wr , or ds active t2 0 ns delay time from rd or ds active to d[15:0] valid without rdy/ ack handshake t3a 65 ns delay time from rdy or ack active to d[15:0] valid t3b 20 ns hold time from rd , wr , or ds inactive to cs inactive t4 0 ns delay from cs , rd , or ds inactive to d[15:0] invalid (note 3) t5 2 ns wait time from wr or ds active to latch d[15:0] without rdy/ ack handshake t6a 65 ns wait time from rdy or ack active to latch d[15:0] t6b 20 ns d[15:0] setup time to wr or ds inactive t7 10 ns d[15:0] hold time from wr or ds inactive t8 2 ns a[10:0] hold time from wr , rd , or ds inactive t9a 5 ns delay from wr , rd , or ds inactive to ale active t9b 20 ns rd , wr , or ds inactive time t10 75 ns muxed address valid to ale inactive (note 4) t11 10 ns muxed address hold time from ale inactive (note 4) t12 10 ns ale pulse width (note 4) t13 20 ns setup time for ale high or muxed address valid to cs active (notes 4, 5, 6) t14 0 ns delay from cs inactive to d[15:0] disable t15 15 ns delay from cs active to rdy/ ack enable t16 15 ns delay from cs , rd , wr , or ds inactive to rdy/ ack inactive (note 7) t17 2 ns delay from cs inactive to rdy/ ack disable t18 15 ns note 1: d[15:0] loaded with 50pf when tested as outputs. note 2: if a gapped clock is applied on tclk and local loopback is enabled, read cycle time must be extended by the length of the large st tclk gap. note 3: not tested during production test. note 4: in nonmultiplexed bus applications ( figure 11-3 to figure 11-6 ), ale should be wired high. in multiplexed bus applications ( figure 11-7 to figure 11-10 ), a[10:0] should be wired to d[15:0] and the falling edge of ale latches the address. note 5: t14 starts at the occurrence of the rising edge of ale or a[10:0] valid whichever occurs later. note 6: in order to avoid bus contention, during a re ad cycle a[10:0] should be disabled prior to rd or ds being active. note 7: rdy/ack may be disabled (t18) before going inactive (t17). downloaded from: http:///
ds32506/ds32508/ds32512 99 of 130 figure 11-3. parallel cpu interface intel read timing diagram (nonmultiplexed) a[10:0] t2 t1 t4 t9a t3a d[15:0] rdy t16 t5 t3b t18 t17 t15 t10 rd cs wr figure 11-4. parallel cpu interface inte l write timing diagram (nonmultiplexed) a[10:0] t2 t1 t4 t9a t6a d[15:0] rdy t16 t8 t6b t18 t17 t10 t7 rd cs wr downloaded from: http:///
ds32506/ds32508/ds32512 100 of 130 figure 11-5. parallel cpu interface motoro la read timing diagram (nonmultiplexed) a[10:0] t2 t1 t4 t9a t3a d[15:0] rdy t16 t5 t3b t18 t17 t15 t10 ds cs r/w figure 11-6. parallel cpu interface motorola write timing diagram (nonmultiplexed) a[10:0] t2 t1 t4 t9a t6a d[15:0] rdy t16 t8 t6b t18 t17 t10 t7 ds cs r/w downloaded from: http:///
ds32506/ds32508/ds32512 101 of 130 figure 11-7. parallel cpu interface inte l read timing diagram (multiplexed) t2 t4 t3a d[15:0] rdy t16 t5 t3b t18 t17 t15 t10 ale 9b t11 t12 t13 t14 a[10:0] rd cs wr figure 11-8. parallel cpu interface inte l write timing diag ram (multiplexed) t2 t4 t6a d[15:0] rdy t16 t8 t6b t18 t17 t10 t7 a[10:0] ale 9b t11 t12 t13 t14 rd cs wr downloaded from: http:///
ds32506/ds32508/ds32512 102 of 130 figure 11-9. parallel cpu interface motoro la read timing diagram (multiplexed) t2 t4 t3a d[15:0] rdy t16 t5 t3b t18 t17 t15 t10 ale 9b t11 t12 t13 t14 a[10:0] ds cs r/w figure 11-10. parallel cpu interface motoro la write timing diagram (multiplexed) t2 t4 t6a d[15:0] rdy t16 t8 t6b t18 t17 t10 t7 a[10:0] ale 9b t11 t12 t13 t14 ds cs r/w downloaded from: http:///
ds32506/ds32508/ds32512 103 of 130 table 11-9. spi interface timing (vdd18 = 1.8v 5%, vdd33 = 3.3v 5%, avdd = 1.8v 5%, t a = -40c to +85c.) (see figure 11-11 .) (note 1) parameter symbol min typ max units sclk frequency f bus 10 mhz sclk cycle time t cyc 100 ns cs setup to first sclk edge t suc 15 ns cs hold time after last sclk edge t hdc 15 ns sclk high time t clkh 50 ns sclk low time t clkl 50 ns sdi data setup time t sui 5 ns sdi data hold time t hdi 15 ns sdo enable time (high impedance to output active) t en 0 ns sdo disable time (output active to high impedance) t dis 25 ns sdo data valid time t dv 40 ns sdo data hold time after update sclk edge t hdo 5 ns note 1: all timing is specified with 100 pf load on all spi pins. downloaded from: http:///
ds32506/ds32508/ds32512 104 of 130 figure 11-11. spi interface timing diagram c s sclk, cpol=0 sclk, cpol=1 t sui t hdi sdi t cyc t suc t clkh t clkl t clkl t clkh t hdc sdo t en t dv t hdo t dis cpha = 0 cpha = 1 c s sclk, cpol=0 sclk, cpol=1 t cyc t suc t clkh t clkl t clkl t hdc t sui t hdi sdi sdo t en t dv t hdo t dis t clkh downloaded from: http:///
ds32506/ds32508/ds32512 105 of 130 table 11-10. jtag interface timing (vdd18 = 1.8v 5%, vdd33 = 3.3v 5%, avdd = 1.8v 5%, t a = -40c to +85c.) (see figure 11-12 .) parameter symbol min typ max units jtclk clock period t1 1000 ns jtclk clock high/low time (note 1) t2/t3 50 500 ns jtclk to jtdi , jtms setup time t4 50 ns jtclk to jtdi , jtms hold time t5 50 ns jtclk to jtdo delay t6 2 50 ns jtclk to jtdo high-z delay (note 2) t7 2 50 ns jtrst width low time t8 100 ns note 1: clock can be stopped high or low. note 2: not tested during production test. figure 11-12. jtag timing diagram t1 jtdo t4 t5 t2 t3 t7 jtdi jtms jtrst t6 t8 jtclk jtrst downloaded from: http:///
ds32506/ds32508/ds32512 106 of 130 12. pin assignments table 12-1. pin assignments sorted by signal name for ds 32506/ds32508/ ds32512 signal ball signal ball signal ball signal ball a0 v5 rclk8 n16 tcc c6 tvss4 p6 a1/lb5[1] t8 rclk9 h11 tclk1 l16 tvss4 u3 a2/lb6[1] w5 rclk10 t20 tclk2 r22 tvss4 v1 a3/lb7[1] r9 rclk11 g18 tclk3 k18 tvss5 c9 a4/lb8[1] y4 rclk12 r18 tclk4 m17 tvss5 e9 a5/lb9[1] p9 rclki a3 tclk5 j18 tvss5 f10 a6/lb10[1] aa3 rd / ds r11 tclk6 t21 tvss6 u10 a7/lb11[1] t9 rdy/ ack u8 tclk7 g21 tvss6 v8 a8/lb12[1] ab2 refclk l22 tclk8 p17 tvss6 v9 a9/itre r10 resref l2 tclk9 h15 tvss7 c12 a10 w6 rlos1 k19 tclk10 u20 tvss7 d11 aist e7 rlos2 p22 tclk11 e20 tvss7 f12 ale t10 rlos3 f22 tclk12 t17 tvss8 t12 cladbyp g7 rlos4 v22 tclki c5 tvss8 v12 clka m21 rlos5 h19 tdm1 k21 tvss8 y12 clkb m22 rlos6 m14 tdm2 p21 tvss9 d14 clkc m19 rlos7 h16 tdm3 k15 tvss9 e15 clkd m20 rlos8 w21 tdm4 p19 tvss9 f14 cs y5 rlos9 d20 tdm5 j20 tvss10 u14 cvdd l18 rlos10 p14 tdm6 n17 tvss10 v15 cvdd l19 rlos11 h9 tdm7 h14 tvss10 y16 cvss l20 rlos12 r13 tdm8 y21 tvss11 c18 d0/lb1[0]/sdo t5 rmon1 l6 tdm9 b22 tvss11 c19 d1/lb2[0]/sdi t6 rmon2 r4 tdm10 u19 tvss11 f16 d2/lb3[0]/sclk r5 rmon3 f2 tdm11 h10 tvss12 u16 d3/lb4[0] r6 rmon4 aa1 tdm12 t16 tvss12 v18 d4/lb5[0] t7 rmon5 d8 test e4 tvss12 y20 d5/lb6[0] r7 rmon6 v10 tlbo1 l7 txn1 j1 d6/lb7[0]/cpha v4 rmon7 a10 tlbo2 m9 txn1 j2 d7/lb8[0]/cpol p7 rmon8 v13 tlbo3 k8 txn2 p1 d8/lb9[0] u5 rmon9 b14 tlbo4 n5 txn2 p2 d9/lb10[0] w4 rmon10 w16 tlbo5 d10 txn3 d1 d10/lb11[0] y3 rmon11 a18 tlbo6 y7 txn3 d2 d11/lb12[0] n8 rmon12 w19 tlbo7 e13 txn4 w1 d12/lb1[1] aa2 rneg1 k17 tlbo8 ab10 txn4 w2 d13/lb1[2] p8 rneg2 n21 tlbo9 d16 txn5 a7 d14/lb1[3] ab1 rneg3 e22 tlbo10 aa14 txn5 b7 d15/lb1[4] r8 rneg4 l14 tlbo11 f17 txn6 aa8 gpioa1/lm1[1] j5 rneg5 j17 tlbo12 t14 txn6 ab8 gpioa2/lm2[1] m7 rneg6 y22 tneg1 j22 txn7 a12 downloaded from: http:///
ds32506/ds32508/ds32512 107 of 130 signal ball signal ball signal ball signal ball gpioa3/lm3[1] j7 rneg7 h18 tneg2 m18 txn7 b12 gpioa4/lm4[1] n6 rneg8 n15 tneg3 k20 txn8 aa12 gpioa5/lm5[1] f8 rneg9 h12 tneg4 w22 txn8 ab12 gpioa6/lm6[1] u11 rneg10 w20 tneg5 j19 txn9 a16 gpioa7/lm7[1] f11 rneg11 g17 tneg6 v21 txn9 b16 gpioa8/lm8[1] u13 rneg12 r17 tneg7 e21 txn10 aa16 gpioa9/lm9[1] f13 rpd b3 tneg8 aa22 txn10 ab16 gpioa10/lm10[1] y14 rpos1 j21 tneg9 c21 txn11 a20 gpioa11/lm11[1] f15 rpos2 l17 tneg10 r15 txn11 b20 gpioa12/lm12[1] y18 rpos3 j15 tneg11 f19 txn12 aa20 gpiob1/lm1[0] g2 rpos4 u22 tneg12 t18 txn12 ab20 gpiob2/lm2[0] m4 rpos5 h20 toe1 k22 txp1 h1 gpiob3/lm3[0] g5 rpos6 p20 toe2 t22 txp1 h2 gpiob4/lm4[0] t1 rpos7 h17 toe3 g22 txp2 n1 gpiob5/lm5[0] e8 rpos8 r20 toe4 m16 txp2 n2 gpiob6/lm6[0] y10 rpos9 f18 toe5 c22 txp3 c1 gpiob7/lm7[0] b10 rpos10 t19 toe6 r19 txp3 c2 gpiob8/lm8[0] ab14 rpos11 g16 toe7 f21 txp4 u1 gpiob9/lm9[0] a14 rpos12 r16 toe8 p16 txp4 u2 gpiob10/lm10[0] r12 rst c3 toe9 d21 txp5 a8 gpiob11/lm11[0] b18 rvdd1 l4 toe10 v19 txp5 b8 gpiob12/lm12[0] u15 rvdd2 p3 toe11 f20 txp6 aa7 hiz j8 rvdd3 g4 toe12 u17 txp6 ab7 hw b1 rvdd4 v3 tpd d6 txp7 a13 ifsel0 u9 rvdd5 c8 tpos1 l15 txp7 b13 ifsel1 y6 rvdd6 y9 tpos2 n19 txp8 aa11 ifsel2 w7 rvdd7 c11 tpos3 h21 txp8 ab11 int ab3 rvdd8 y13 tpos4 m15 txp9 a17 jad0 g8 rvdd9 e14 tpos5 j16 txp9 b17 jad1 c4 rvdd10 v16 tpos6 u21 txp10 aa15 jas0 f7 rvdd11 d17 tpos7 g20 txp10 ab15 jas1 e5 rvdd12 u18 tpos8 p15 txp11 a21 jtclk d4 rvss1 l1 tpos9 h13 txp11 b21 jtdi d3 rvss2 p5 tpos10 v20 txp12 aa19 jtdo f6 rvss3 f5 tpos11 e19 txp12 ab19 jtms h7 rvss4 w3 tpos12 r14 vdd18 c10 jtrst e3 rvss5 c7 tvdd1 j3 vdd18 c17 jvdd1 h3 rvss6 w10 tvdd1 k4 vdd18 g1 jvdd2 m1 rvss7 e11 tvdd1 k5 vdd18 h22 jvdd3 a1 rvss8 w13 tvdd2 m3 vdd18 n20 jvdd4 t4 rvss9 c14 tvdd2 m6 vdd18 t2 jvdd5 e10 rvss10 y17 tvdd2 n3 vdd18 aa10 jvdd6 aa6 rvss11 e17 tvdd3 a2 vdd18 aa18 jvdd7 d13 rvss12 ab22 tvdd3 f4 vdd33 j10 downloaded from: http:///
ds32506/ds32508/ds32512 108 of 130 signal ball signal ball signal ball signal ball jvdd8 w11 rxn1 k1 tvdd3 k6 vdd33 j13 jvdd9 e16 rxn2 r2 tvdd4 n7 vdd33 k9 jvdd10 w14 rxn3 e1 tvdd4 u4 vdd33 k14 jvdd11 e18 rxn4 y2 tvdd4 v2 vdd33 n9 jvdd12 v17 rxn5 b6 tvdd5 b9 vdd33 n14 jvss1 h4 rxn6 ab9 tvdd5 d9 vdd33 p10 jvss2 m2 rxn7 a11 tvdd5 f9 vdd33 p13 jvss3 b2 rxn8 ab13 tvdd6 p11 vss a22 jvss4 t3 rxn9 a15 tvdd6 v7 vss j6 jvss5 a9 rxn10 aa17 tvdd6 y8 vss j9 jvss6 ab6 rxn11 a19 tvdd7 d12 vss j11 jvss7 c13 rxn12 aa21 tvdd7 e12 vss j12 jvss8 v11 rxp1 k2 tvdd7 g10 vss k7 jvss9 c16 rxp2 r1 tvdd8 u12 vss k10 jvss10 v14 rxp3 e2 tvdd8 w12 vss k11 jvss11 d19 rxp4 y1 tvdd8 y11 vss k12 jvss12 w17 rxp5 a6 tvdd9 c15 vss k13 lbs h8 rxp6 aa9 tvdd9 d15 vss l5 mt0 l21 rxp7 b11 tvdd9 g12 vss l8 mt1 d5 rxp8 aa13 tvdd10 t13 vss l9 mt2 g6 rxp9 b15 tvdd10 w15 vss l10 mt3 aa4 rxp10 ab17 tvdd10 y15 vss l11 mt4 ab4 rxp11 b19 tvdd11 c20 vss l12 mt5 a4 rxp12 ab21 tvdd11 d18 vss l13 mt6 b4 tais1 f1 tvdd11 g14 vss m10 mt7 aa5 tais2 l3 tvdd12 t15 vss m11 mt8 ab5 tais3 h6 tvdd12 w18 vss m12 mt9 a5 tais4 r3 tvdd12 y19 vss m13 mt10 b5 tais5 g9 tvss1 j4 vss n10 rbin e6 tais6 w8 tvss1 k3 vss n11 rclk1 k16 tais7 g11 tvss1 m8 vss n12 rclk2 n22 tais8 t11 tvss2 m5 vss n13 rclk3 d22 tais9 g13 tvss2 n4 vss p18 rclk4 n18 tais10 p12 tvss2 p4 vss u6 rclk5 j14 tais11 g15 tvss3 f3 vss u7 rclk6 r21 tais12 ab18 tvss3 g3 vss w9 rclk7 g19 tbin d7 tvss3 h5 wr /r/ w v6 note: there are two txp leads and two txn leads for each liu port. fo r best performance, the two txp leads must be wired together and the two txn leads must be wired together on each port. downloaded from: http:///
ds32506/ds32508/ds32512 109 of 130 figure 12-1. ds32512 pin a ssignment, hardware a nd microprocessor interfaces left half 1 2 3 4 5 6 7 8 9 10 11 a jvdd3 tvdd3 rclki mt5 mt9 rxp5 txn5 txp5 jvss5 rmon7 rxn7 b hw jvss3 rpd mt6 mt10 rxn5 txn5 txp5 tvdd5 gpiob7 rxp7 c txp3 txp3 rst jad1 tclki tcc rvss5 rvdd5 tvss5 vdd18 rvdd7 d txn3 txn3 jtdi jtclk mt1 tpd tbin rmon5 tvdd5 tlbo5 tvss7 e rxn3 rxp3 jtrst test jas1 rbin aist gpiob5 tvss5 jvdd5 rvss7 f tais1 rmon3 tvss3 tvdd3 rvss3 jtdo jas0 gpioa5 tvdd5 tvss5 gpioa7 g vdd18 gpiob1 tvss3 rvdd3 gpiob3 mt2 cladbyp jad0 tais5 tvdd7 tais7 h txp1 txp1 jvdd1 jvss1 tvss3 tais3 jtms lbs rlos11 tdm11 rclk9 j txn1 txn1 tvdd1 tvss1 gpioa1 vss gpioa3 hiz vss vdd33 vss k rxn1 rxp1 tvss1 tvdd1 tvdd1 tvdd3 vss tlbo3 vdd33 vss vss l rvss1 resref tais2 rvdd1 vss rmon1 tlbo1 vss vss vss vss m jvdd2 jvss2 tvdd2 gpiob2 tvss2 tvdd2 gpioa2 tvss1 tlbo2 vss vss n txp2 txp2 tvdd2 tvss2 tlbo4 gpioa4 tvdd4 d11 vdd33 vss vss p txn2 txn2 rvdd2 tvss2 rvss2 tvss4 d7/cpol d13 a5 vdd33 tvdd6 r rxp2 rxn2 tais4 rmon2 d2/sclk d3 d5 d15 a3 a9 rd / ds t gpiob4 vdd18 jvss4 jvdd4 d0/sdo d1/sdi d4 a1 a7 ale tais8 u txp4 txp4 tvss4 tvdd4 d8 vss vss rdy/ ack ifsel0 tvss6 gpioa6 v tvss4 tvdd4 rvdd4 d6/cpha a0 wr/ r/ w tvdd6 tvss6 tvss6 rmon6 jvss8 w txn4 txn4 rvss4 d9 a2 a10 ifsel2 tais6 vss rvss6 jvdd8 y rxp4 rxn4 d10 a4 cs ifsel1 tlbo6 tvdd6 rvdd6 gpiob6 tvdd8 aa rmon4 d12 a6 mt3 mt7 jvdd6 txp6 txn6 rxp6 vdd18 txp8 ab d14 a8 int mt4 mt8 jvss6 txp6 txn6 rxn6 tlbo8 txp8 1 2 3 4 5 6 7 8 9 10 11 high-speed analog low-speed analog high-speed digital low-speed digital n.c. and manufacturing test vdd 1.8v vddio 3.3v analog vss analog vdd 1.8v vss downloaded from: http:///
ds32506/ds32508/ds32512 110 of 130 right half 12 13 14 15 16 17 18 19 20 21 22 txn7 txp7 gpiob9 rxn9 txn9 txp9 rmon11 rxn11 txn11 txp11 vss a txn7 txp7 rmon9 rxp9 txn9 txp9 gpiob11 rxp11 txn11 txp11 tdm9 b tvss7 jvss7 rvss9 tvdd9 jvss9 vdd18 tvss11 tvss11 tvdd11 tneg9 toe5 c tvdd7 jvdd7 tvss9 tvdd9 tlbo9 rvdd11 tvdd11 jvss11 rlos9 toe9 rclk3 d tvdd7 tlbo7 rvdd9 tvss9 jvdd9 rvss11 jvdd11 tpos11 tclk11 tneg7 rneg3 e tvss7 gpioa9 tvss9 gpioa11 tvss11 tlbo11 rpos9 tneg11 toe11 toe7 rlos3 f tvdd9 tais9 tvdd11 tais11 rpos11 rneg11 rclk11 rclk7 tpos7 tclk7 toe3 g rneg9 tpos9 tdm7 tclk9 rlos7 rpos7 rneg7 rlos5 rpos5 tpos3 vdd18 h vss vdd33 rclk5 rpos3 tpos5 rneg5 tclk5 tneg5 tdm5 rpos1 tneg1 j vss vss vdd33 tdm3 rclk1 rneg1 tclk3 rlos1 tneg3 tdm1 toe1 k vss vss rneg4 tpos1 tclk1 rpos2 cvdd cvdd cvss mt0 refclk l vss vss rlos6 tpos4 toe4 tclk4 tneg2 clkc clkd clka clkb m vss vss vdd33 rneg8 rclk8 tdm6 rclk4 tpos2 vdd18 rneg2 rclk2 n tais10 vdd33 rlos10 tpos8 toe8 tclk8 vss tdm4 rpos6 tdm2 rlos2 p gpiob10 rlos12 tpos12 tneg10 rpos12 rneg12 rclk12 toe6 rpos8 rclk6 tclk2 r tvss8 tvdd10 tlbo12 tvdd12 tdm12 tclk12 tneg12 rpos10 rclk10 tclk6 toe2 t tvdd8 gpioa8 tvss10 gpiob12 tvss12 toe12 rvdd12 tdm10 tclk10 tpos6 rpos4 u tvss8 rmon8 jvss10 tvss10 rvdd10 jvdd12 tvss12 toe10 tpos10 tneg6 rlos4 v tvdd8 rvss8 jvdd10 tvdd10 rmon10 jvss12 tvdd12 rmon12 rneg10 rlos8 tneg4 w tvss8 rvdd8 gpioa10 tvdd10 tvss10 rvss10 gpioa12 tvdd12 tvss12 tdm8 rneg6 y txn8 rxp8 tlbo10 txp10 txn10 rxn10 vdd18 txp12 txn12 rxn12 tneg8 aa txn8 rxn8 gpiob8 txp10 txn10 rxp10 tais12 txp12 txn12 rxp12 rvss12 ab 12 13 14 15 16 17 18 19 20 21 22 high-speed analog low-speed analog high-speed digital low-speed digital n.c. and manufacturing test vdd 1.8v vddio 3.3v analog vss analog vdd 1.8v vss downloaded from: http:///
ds32506/ds32508/ds32512 111 of 130 figure 12-2. ds32512 pin assignmen t, hardware interface only left half 1 2 3 4 5 6 7 8 9 10 11 a jvdd3 tvdd3 rclki mt5 mt9 rxp5 txn5 txp5 jvss5 rmon7 rxn7 b hw jvss3 rpd mt6 mt10 rxn5 txn5 txp5 tvdd5 lm7[0] rxp7 c txp3 txp3 rst jad1 tclki tcc rvss5 rvdd5 tvss5 vdd18 rvdd7 d txn3 txn3 jtdi jtclk mt1 tpd tbin rmon5 tvdd5 tlbo5 tvss7 e rxn3 rxp3 jtrst test jas1 rbin aist lm5[0] tvss5 jvdd5 rvss7 f tais1 rmon3 tvss3 tvdd3 rvss3 jtdo jas0 lm5[1] tvdd5 tvss5 lm7[1] g vdd18 lm1[0] tvss3 rvdd3 lm3[0] mt2 cladbyp jad0 tais5 tvdd7 tais7 h txp1 txp1 jvdd1 jvss1 tvss3 tais3 jtms lbs rlos11 tdm11 rclk9 j txn1 txn1 tvdd1 tvss1 lm1[1] vss lm3[1] hiz vss vdd33 vss k rxn1 rxp1 tvss1 tvdd1 tvdd1 tvdd3 vss tlbo3 vdd33 vss vss l rvss1 resref tais2 rvdd1 vss rmon1 tlbo1 vss vss vss vss m jvdd2 jvss2 tvdd2 lm2[0] tvss2 tvdd2 lm2[1] tvss1 tlbo2 vss vss n txp2 txp2 tvdd2 tvss2 tlbo4 lm4[1] tvdd4 lb12[0] vdd33 vss vss p txn2 txn2 rvdd2 tvss2 rvss2 tvss4 lb8[0] lb2[1] lb9[1] vdd33 tvdd6 r rxp2 rxn2 tais4 rmon2 lb3[0] lb4[0] lb6[0] lb4[1] lb7[1] itre n.c. t lm4[0] vdd18 jvss4 jvdd4 lb1[0] lb2[0] lb5[0] lb5[1] lb11[1] n.c. tais8 u txp4 txp4 tvss4 tvdd4 lb9[0] vss vss n.c. ifsel0 tvss6 lm6[1] v tvss4 tvdd4 rvdd4 lb7[0] n.c. n.c. tvdd6 tvss6 tvss6 rmon6 jvss8 w txn4 txn4 rvss4 lb10[0] lb6[1] n.c. ifsel2 tais6 vss rvss6 jvdd8 y rxp4 rxn4 lb11[0] lb8[1] n.c. ifsel1 tlbo6 tvdd6 rvdd6 lm6[0] tvdd8 aa rmon4 lb1[1] lb10[1] mt3 mt7 jvdd6 txp6 txn6 rxp6 vdd18 txp8 ab lb3[1] lb12[1] n.c. mt4 mt8 jvss6 txp6 txn6 rxn6 tlbo8 txp8 1 2 3 4 5 6 7 8 9 10 11 high-speed analog low-speed analog high-speed digital low-speed digital n.c. and manufacturing test vdd 1.8v vddio 3.3v analog vss analog vdd 1.8v vss downloaded from: http:///
ds32506/ds32508/ds32512 112 of 130 right half 12 13 14 15 16 17 18 19 20 21 22 txn7 txp7 lm9[0] rxn9 txn9 txp9 rmon11 rxn11 txn11 txp11 vss a txn7 txp7 rmon9 rxp9 txn9 txp9 lm11[0] rxp11 txn11 txp11 tdm9 b tvss7 jvss7 rvss9 tvdd9 jvss9 vdd18 tvss11 tvss11 tvdd11 tneg9 toe5 c tvdd7 jvdd7 tvss9 tvdd9 tlbo9 rvdd11 tvdd11 jvss11 rlos9 toe9 rclk3 d tvdd7 tlbo7 rvdd9 tvss9 jvdd9 rvss11 jvdd11 tpos11 tclk11 tneg7 rneg3 e tvss7 lm9[1] tvss9 lm11[1] tvss11 tlbo11 rpos9 tneg11 toe11 toe7 rlos3 f tvdd9 tais9 tvdd11 tais11 rpos11 rneg11 rclk11 rclk7 tpos7 tclk7 toe3 g rneg9 tpos9 tdm7 tclk9 rlos7 rpos7 rneg7 rlos5 rpos5 tpos3 vdd18 h vss vdd33 rclk5 rpos3 tpos5 rneg5 tclk5 tneg5 tdm5 rpos1 tneg1 j vss vss vdd33 tdm3 rclk1 rneg1 tclk3 rlos1 tneg3 tdm1 toe1 k vss vss rneg4 tpos1 tclk1 rpos2 cvdd cvdd cvss mt0 refclk l vss vss rlos6 tpos4 toe4 tclk4 tneg2 clkc clkd clka clkb m vss vss vdd33 rneg8 rclk8 tdm6 rclk4 tpos2 vdd18 rneg2 rclk2 n tais10 vdd33 rlos10 tpos8 toe8 tclk8 vss tdm4 rpos6 tdm2 rlos2 p lm10[0] rlos12 tpos12 tneg10 rpos12 rneg12 rclk12 toe6 rpos8 rclk6 tclk2 r tvss8 tvdd10 tlbo12 tvdd12 tdm12 tclk12 tneg12 rpos10 rclk10 tclk6 toe2 t tvdd8 lm8[1] tvss10 lm12[0] tvss12 toe12 rvdd12 tdm10 tclk10 tpos6 rpos4 u tvss8 rmon8 jvss10 tvss10 rvdd10 jvdd12 tvss12 toe10 tpos10 tneg6 rlos4 v tvdd8 rvss8 jvdd10 tvdd10 rmon10 jvss12 tvdd12 rmon12 rneg10 rlos8 tneg4 w tvss8 rvdd8 lm10[1] tvdd10 tvss10 rvss10 lm12[1] tvdd12 tvss12 tdm8 rneg6 y txn8 rxp8 tlbo10 txp10 txn10 rxn10 vdd18 txp12 txn12 rxn12 tneg8 aa txn8 rxn8 lm8[0] txp10 txn10 rxp10 tais12 txp12 txn12 rxp12 rvss12 ab 12 13 14 15 16 17 18 19 20 21 22 high-speed analog low-speed analog high-speed digital low-speed digital n.c. and manufacturing test vdd 1.8v vddio 3.3v analog vss analog vdd 1.8v vss downloaded from: http:///
ds32506/ds32508/ds32512 113 of 130 figure 12-3. ds32512 pin assignment, microprocessor interface only left half 1 2 3 4 5 6 7 8 9 10 11 a jvdd3 tvdd3 n.c. mt5 mt9 rxp5 txn5 txp5 jvss5 n.c. rxn7 b hw jvss3 n.c. mt6 mt10 rxn5 txn5 txp5 tvdd5 gpiob7 rxp7 c txp3 txp3 rst n.c. n.c. n.c. rvss5 rvdd5 tvss5 vdd18 rvdd7 d txn3 txn3 jtdi jtclk mt1 n.c. n.c. n.c. tvdd5 n.c. tvss7 e rxn3 rxp3 jtrst test n.c. n.c. n.c. gpiob5 tvss5 jvdd5 rvss7 f n.c. n.c. tvss3 tvdd3 rvss3 jtdo n.c. gpioa5 tvdd5 tvss5 gpioa7 g vdd18 gpiob1 tvss3 rvdd3 gpiob3 mt2 cladbyp n.c. n.c. tvdd7 n.c. h txp1 txp1 jvdd1 jvss1 tvss3 n.c. jtms n.c. n.c. n.c. rclk9 j txn1 txn1 tvdd1 tvss1 gpioa1 vss gpioa3 hiz vss vdd33 vss k rxn1 rxp1 tvss1 tvdd1 tvdd1 tvdd3 vss n.c. vdd33 vss vss l rvss1 resref n.c. rvdd1 vss n.c. n.c. vss vss vss vss m jvdd2 jvss2 tvdd2 gpiob2 tvss2 tvdd2 gpioa2 tvss1 n.c. vss vss n txp2 txp2 tvdd2 tvss2 n.c. gpioa4 tvdd4 d11 vdd33 vss vss p txn2 txn2 rvdd2 tvss2 rvss2 tvss4 d7/cpol d13 a5 vdd33 tvdd6 r rxp2 rxn2 n.c. n.c. d2/sclk d3 d5 d15 a3 a9 rd/ds t gpiob4 vdd18 jvss4 jvdd4 d0/sdo d1/sdi d4 a1 a7 ale n.c. u txp4 txp4 tvss4 tvdd4 d8 vss vss rdy/ ack ifsel0 tvss6 gpioa6 v tvss4 tvdd4 rvdd4 d6/cpha a0 wr/ r/ w tvdd6 tvss6 tvss6 n.c. jvss8 w txn4 txn4 rvss4 d9 a2 a10 ifsel2 n.c. vss rvss6 jvdd8 y rxp4 rxn4 d10 a4 cs ifsel1 n.c. tvdd6 rvdd6 gpiob6 tvdd8 aa n.c. d12 a6 mt3 mt7 jvdd6 txp6 txn6 rxp6 vdd18 txp8 ab d14 a8 int mt4 mt8 jvss6 txp6 txn6 rxn6 n.c. txp8 1 2 3 4 5 6 7 8 9 10 11 high-speed analog low-speed analog high-speed digital low-speed digital n.c. and manufacturing test vdd 1.8v vddio 3.3v analog vss analog vdd 1.8v vss downloaded from: http:///
ds32506/ds32508/ds32512 114 of 130 right half 12 13 14 15 16 17 18 19 20 21 22 txn7 txp7 gpiob9 rxn9 txn9 txp9 n.c. rxn11 txn11 txp11 vss a txn7 txp7 n.c. rxp9 txn9 txp9 gpiob11 rxp11 txn11 txp11 n.c. b tvss7 jvss7 rvss9 tvdd9 jvss9 vdd18 tvss11 tvss11 tvdd11 tneg9 n.c. c tvdd7 jvdd7 tvss9 tvdd9 n.c. rvdd11 tvdd11 jvss11 n.c. n.c. rclk3 d tvdd7 n.c. rvdd9 tvss9 jvdd9 rvss11 jvdd11 tpos11 tclk11 tneg7 rneg3 e tvss7 gpioa9 tvss9 gpioa11 tvss11 n.c. rpos9 tneg11 n.c. n.c. n.c. f tvdd9 n.c. tvdd11 n.c. rpos11 rneg11 rclk11 rclk7 tpos7 tclk7 n.c. g rneg9 tpos9 n.c. tclk9 n.c. rpos7 rneg7 n.c. rpos5 tpos3 vdd18 h vss vdd33 rclk5 rpos3 tpos5 rneg5 tclk5 tneg5 n.c. rpos1 tneg1 j vss vss vdd33 n.c. rclk1 rneg1 tclk3 n.c. tneg3 n.c. n.c. k vss vss rneg4 tpos1 tclk1 rpos2 cvdd cvdd cvss mt0 refclk l vss vss n.c. tpos4 n.c. tclk4 tneg2 clkc clkd clka clkb m vss vss vdd33 rneg8 rclk8 n.c. rclk4 tpos2 vdd18 rneg2 rclk2 n n.c. vdd33 n.c. tpos8 n.c. tclk8 vss n.c. rpos6 n.c. n.c. p gpiob10 n.c. tpos12 tneg10 rpos12 rneg12 rclk12 n.c. rpos8 rclk6 tclk2 r tvss8 tvdd10 n.c. tvdd12 n.c. tclk12 tneg12 rpos10 rclk10 tclk6 n.c. t tvdd8 gpioa8 tvss10 gpiob12 tvss12 n.c. rvdd12 n.c. tclk10 tpos6 rpos4 u tvss8 n.c. jvss10 tvss10 rvdd10 jvdd12 tvss12 n.c. tpos10 tneg6 n.c. v tvdd8 rvss8 jvdd10 tvdd10 n.c. jvss12 tvdd12 n.c. rneg10 n.c. tneg4 w tvss8 rvdd8 gpioa10 tvdd10 tvss10 rvss10 gpioa12 tvdd12 tvss12 n.c. rneg6 y txn8 rxp8 n.c. txp10 txn10 rxn10 vdd18 txp12 txn12 rxn12 tneg8 aa txn8 rxn8 gpiob8 txp10 txn10 rxp10 n.c. txp12 txn12 rxp12 rvss12 ab 12 13 14 15 16 17 18 19 20 21 22 high-speed analog low-speed analog high-speed digital low-speed digital n.c. and manufacturing test vdd 1.8v vddio 3.3v analog vss analog vdd 1.8v vss downloaded from: http:///
ds32506/ds32508/ds32512 115 of 130 figure 12-4. ds32508 pin a ssignment, hardware a nd microprocessor interfaces left half 1 2 3 4 5 6 7 8 9 10 11 a jvdd3 tvdd3 rclki mt5 n.c. rxp5 txn5 txp5 jvss5 rmon7 rxn7 b hw jvss3 rpd mt6 n.c. rxn5 txn5 txp5 tvdd5 gpiob7 rxp7 c txp3 txp3 rst jad1 tclki tcc rvss5 rvdd5 tvss5 vdd18 rvdd7 d txn3 txn3 jtdi jtclk mt1 tpd tbin rmon5 tvdd5 tlbo5 tvss7 e rxn3 rxp3 jtrst test jas1 rbin aist gpiob5 tvss5 jvdd5 rvss7 f tais1 rmon3 tvss3 tvdd3 rvss3 jtdo jas0 gpioa5 tvdd5 tvss5 gpioa7 g vdd18 gpiob1 tvss3 rvdd3 gpiob3 mt2 cladbyp jad0 tais5 tvdd7 tais7 h txp1 txp1 jvdd1 jvss1 tvss3 tais3 jtms lbs n.c. n.c. n.c. j txn1 txn1 tvdd1 tvss1 gpioa1 vss gpioa3 hiz vss vdd33 vss k rxn1 rxp1 tvss1 tvdd1 tvdd1 tvdd3 vss tlbo3 vdd33 vss vss l rvss1 resref tais2 rvdd1 vss rmon1 tlbo1 vss vss vss vss m jvdd2 jvss2 tvdd2 gpiob2 tvss2 tvdd2 gpioa2 tvss1 tlbo2 vss vss n txp2 txp2 tvdd2 tvss2 tlbo4 gpioa4 tvdd4 d11 vdd33 vss vss p txn2 txn2 rvdd2 tvss2 rvss2 tvss4 d7/cpol d13 a5 vdd33 tvdd6 r rxp2 rxn2 tais4 rmon2 d2/sclk d3 d5 d15 a3 a9 rd/ds t gpiob4 vdd18 jvss4 jvdd4 d0/sdo d1/sdi d4 a1 a7 ale tais8 u txp4 txp4 tvss4 tvdd4 d8 vss vss rdy/ ack ifsel0 tvss6 gpioa6 v tvss4 tvdd4 rvdd4 d6/cpha a0 wr/ r/ w tvdd6 tvss6 tvss6 rmon6 jvss8 w txn4 txn4 rvss4 d9 a2 a10 ifsel2 tais6 vss rvss6 jvdd8 y rxp4 rxn4 d10 a4 cs ifsel1 tlbo6 tvdd6 rvdd6 gpiob6 tvdd8 aa rmon4 d12 a6 mt3 mt7 jvdd6 txp6 txn6 rxp6 vdd18 txp8 ab d14 a8 int mt4 mt8 jvss6 txp6 txn6 rxn6 tlbo8 txp8 1 2 3 4 5 6 7 8 9 10 11 high-speed analog low-speed analog high-speed digital low-speed digital n.c. and manufacturing test vdd 1.8v vddio 3.3v analog vss analog vdd 1.8v vss downloaded from: http:///
ds32506/ds32508/ds32512 116 of 130 right half 12 13 14 15 16 17 18 19 20 21 22 txn7 txp7 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. vss a txn7 txp7 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. b tvss7 jvss7 vss vss vss vdd18 vss vss vss n.c. toe5 c tvdd7 jvdd7 vss vss n.c. vss vss vss n.c. n.c. rclk3 d tvdd7 tlbo7 vss vss vss vss vss n.c. n.c. tneg7 rneg3 e tvss7 n.c. vss n.c. vss n.c. n.c. n.c. n.c. toe7 rlos3 f vss n.c. vss n.c. n.c. n.c. n.c. rclk7 tpos7 tclk7 toe3 g n.c. n.c. tdm7 n.c. rlos7 rpos7 rneg7 rlos5 rpos5 tpos3 vdd18 h vss vdd33 rclk5 rpos3 tpos5 rneg5 tclk5 tneg5 tdm5 rpos1 tneg1 j vss vss vdd33 tdm3 rclk1 rneg1 tclk3 rlos1 tneg3 tdm1 toe1 k vss vss rneg4 tpos1 tclk1 rpos2 cvdd cvdd cvss mt0 refclk l vss vss rlos6 tpos4 toe4 tclk4 tneg2 clkc clkd clka clkb m vss vss vdd33 rneg8 rclk8 tdm6 rclk4 tpos2 vdd18 rneg2 rclk2 n n.c. vdd33 n.c. tpos8 toe8 tclk8 vss tdm4 rpos6 tdm2 rlos2 p n.c. n.c. n.c. n.c. n.c. n.c. n.c. toe6 rpos8 rclk6 tclk2 r tvss8 vss n.c. vss n.c. n.c. n.c. n.c. n.c. tclk6 toe2 t tvdd8 gpioa8 vss n.c. vss n.c. vss n.c. n.c. tpos6 rpos4 u tvss8 rmon8 vss vss vss vss vss n.c. n.c. tneg6 rlos4 v tvdd8 rvss8 vss vss n.c. vss vss n.c. n.c. rlos8 tneg4 w tvss8 rvdd8 n.c. vss vss vss n.c. vss vss tdm8 rneg6 y txn8 rxp8 n.c. n.c. n.c. n.c. vdd18 n.c. n.c. n.c. tneg8 aa txn8 rxn8 gpiob8 n.c. n.c. n.c. n.c. n.c. n.c. n.c. vss ab 12 13 14 15 16 17 18 19 20 21 22 high-speed analog low-speed analog high-speed digital low-speed digital n.c. and manufacturing test vdd 1.8v vddio 3.3v analog vss analog vdd 1.8v vss downloaded from: http:///
ds32506/ds32508/ds32512 117 of 130 figure 12-5. ds32508 pin assignmen t, hardware interface only left half 1 2 3 4 5 6 7 8 9 10 11 a jvdd3 tvdd3 rclki mt5 n.c. rxp5 txn5 txp5 jvss5 rmon7 rxn7 b hw jvss3 rpd mt6 n.c. rxn5 txn5 txp5 tvdd5 lm7[0] rxp7 c txp3 txp3 rst jad1 tclki tcc rvss5 rvdd5 tvss5 vdd18 rvdd7 d txn3 txn3 jtdi jtclk mt1 tpd tbin rmon5 tvdd5 tlbo5 tvss7 e rxn3 rxp3 jtrst test jas1 rbin aist lm5[0] tvss5 jvdd5 rvss7 f tais1 rmon3 tvss3 tvdd3 rvss3 jtdo jas0 lm5[1] tvdd5 tvss5 lm7[1] g vdd18 lm1[0] tvss3 rvdd3 lm3[0] mt2 cladbyp jad0 tais5 tvdd7 tais7 h txp1 txp1 jvdd1 jvss1 tvss3 tais3 jtms lbs n.c. n.c. n.c. j txn1 txn1 tvdd1 tvss1 lm1[1] vss lm3[1] hiz vss vdd33 vss k rxn1 rxp1 tvss1 tvdd1 tvdd1 tvdd3 vss tlbo3 vdd33 vss vss l rvss1 resref tais2 rvdd1 vss rmon1 tlbo1 vss vss vss vss m jvdd2 jvss2 tvdd2 lm2[0] tvss2 tvdd2 lm2[1] tvss1 tlbo2 vss vss n txp2 txp2 tvdd2 tvss2 tlbo4 lm4[1] tvdd4 n.c. vdd33 vss vss p txn2 txn2 rvdd2 tvss2 rvss2 tvss4 lb8[0] lb2[1] n.c. vdd33 tvdd6 r rxp2 rxn2 tais4 rmon2 lb3[0] lb4[0] lb6[0] lb4[1] lb7[1] itre n.c. t lm4[0] vdd18 jvss4 jvdd4 lb1[0] lb2[0] lb5[0] lb5[1] n.c. n.c. tais8 u txp4 txp4 tvss4 tvdd4 n.c. vss vss n.c. ifsel0 tvss6 lm6[1] v tvss4 tvdd4 rvdd4 lb7[0] n.c. n.c. tvdd6 tvss6 tvss6 rmon6 jvss8 w txn4 txn4 rvss4 n.c. lb6[1] n.c. ifsel2 tais6 vss rvss6 jvdd8 y rxp4 rxn4 n.c. lb8[1] n.c. ifsel1 tlbo6 tvdd6 rvdd6 lm6[0] tvdd8 aa rmon4 lb1[1] n.c. mt3 mt7 jvdd6 txp6 txn6 rxp6 vdd18 txp8 ab lb3[1] n.c. n.c. mt4 mt8 jvss6 txp6 txn6 rxn6 tlbo8 txp8 1 2 3 4 5 6 7 8 9 10 11 high-speed analog low-speed analog high-speed digital low-speed digital n.c. and manufacturing test vdd 1.8v vddio 3.3v analog vss analog vdd 1.8v vss downloaded from: http:///
ds32506/ds32508/ds32512 118 of 130 right half 12 13 14 15 16 17 18 19 20 21 22 txn7 txp7 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. vss a txn7 txp7 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. b tvss7 jvss7 vss vss vss vdd18 vss vss vss n.c. toe5 c tvdd7 jvdd7 vss vss n.c. vss vss vss n.c. n.c. rclk3 d tvdd7 tlbo7 vss vss vss vss vss n.c. n.c. tneg7 rneg3 e tvss7 n.c. vss n.c. vss n.c. n.c. n.c. n.c. toe7 rlos3 f vss n.c. vss n.c. n.c. n.c. n.c. rclk7 tpos7 tclk7 toe3 g n.c. n.c. tdm7 n.c. rlos7 rpos7 rneg7 rlos5 rpos5 tpos3 vdd18 h vss vdd33 rclk5 rpos3 tpos5 rneg5 tclk5 tneg5 tdm5 rpos1 tneg1 j vss vss vdd33 tdm3 rclk1 rneg1 tclk3 rlos1 tneg3 tdm1 toe1 k vss vss rneg4 tpos1 tclk1 rpos2 cvdd cvdd cvss mt0 refclk l vss vss rlos6 tpos4 toe4 tclk4 tneg2 clkc clkd clka clkb m vss vss vdd33 rneg8 rclk8 tdm6 rclk4 tpos2 vdd18 rneg2 rclk2 n n.c. vdd33 n.c. tpos8 toe8 tclk8 vss tdm4 rpos6 tdm2 rlos2 p n.c. n.c. n.c. n.c. n.c. n.c. n.c. toe6 rpos8 rclk6 tclk2 r tvss8 vss n.c. vss n.c. n.c. n.c. n.c. n.c. tclk6 toe2 t tvdd8 lm8[1] vss n.c. vss n.c. vss n.c. n.c. tpos6 rpos4 u tvss8 rmon8 vss vss vss vss vss n.c. n.c. tneg6 rlos4 v tvdd8 rvss8 vss vss n.c. vss vss n.c. n.c. rlos8 tneg4 w tvss8 rvdd8 n.c. vss vss vss n.c. vss vss tdm8 rneg6 y txn8 rxp8 n.c. n.c. n.c. n.c. vdd18 n.c. n.c. n.c. tneg8 aa txn8 rxn8 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. vss ab 12 13 14 15 16 17 18 19 20 21 22 high-speed analog low-speed analog high-speed digital low-speed digital n.c. and manufacturing test vdd 1.8v vddio 3.3v analog vss analog vdd 1.8v vss downloaded from: http:///
ds32506/ds32508/ds32512 119 of 130 figure 12-6. ds32508 pin assignment, microprocessor interface only left half 1 2 3 4 5 6 7 8 9 10 11 a jvdd3 tvdd3 n.c. mt5 n.c. rxp5 txn5 txp5 jvss5 n.c. rxn7 b hw jvss3 n.c. mt6 n.c. rxn5 txn5 txp5 tvdd5 gpiob7 rxp7 c txp3 txp3 rst n.c. n.c. n.c. rvss5 rvdd5 tvss5 vdd18 rvdd7 d txn3 txn3 jtdi jtclk mt1 n.c. n.c. n.c. tvdd5 n.c. tvss7 e rxn3 rxp3 jtrst test n.c. n.c. n.c. gpiob5 tvss5 jvdd5 rvss7 f n.c. n.c. tvss3 tvdd3 rvss3 jtdo n.c. gpioa5 tvdd5 tvss5 gpioa7 g vdd18 gpiob1 tvss3 rvdd3 gpiob3 mt2 cladbyp n.c. n.c. tvdd7 n.c. h txp1 txp1 jvdd1 jvss1 tvss3 n.c. jtms n.c. n.c. n.c. n.c. j txn1 txn1 tvdd1 tvss1 gpioa1 vss gpioa3 hiz vss vdd33 vss k rxn1 rxp1 tvss1 tvdd1 tvdd1 tvdd3 vss n.c. vdd33 vss vss l rvss1 resref n.c. rvdd1 vss n.c. n.c. vss vss vss vss m jvdd2 jvss2 tvdd2 gpiob2 tvss2 tvdd2 gpioa2 tvss1 n.c. vss vss n txp2 txp2 tvdd2 tvss2 n.c. gpioa4 tvdd4 d11 vdd33 vss vss p txn2 txn2 rvdd2 tvss2 rvss2 tvss4 d7/cpol d13 a5 vdd33 tvdd6 r rxp2 rxn2 n.c. n.c. d2/sclk d3 d5 d15 a3 a9 rd/ds t gpiob4 vdd18 jvss4 jvdd4 d0/sdo d1/sdi d4 a1 a7 ale n.c. u txp4 txp4 tvss4 tvdd4 d8 vss vss rdy/ ack ifsel0 tvss6 gpioa6 v tvss4 tvdd4 rvdd4 d6/cpha a0 wr/ r/ w tvdd6 tvss6 tvss6 n.c. jvss8 w txn4 txn4 rvss4 d9 a2 a10 ifsel2 n.c. vss rvss6 jvdd8 y rxp4 rxn4 d10 a4 cs ifsel1 n.c. tvdd6 rvdd6 gpiob6 tvdd8 aa n.c. d12 a6 mt3 mt7 jvdd6 txp6 txn6 rxp6 vdd18 txp8 ab d14 a8 int mt4 mt8 jvss6 txp6 txn6 rxn6 n.c. txp8 1 2 3 4 5 6 7 8 9 10 11 high-speed analog low-speed analog high-speed digital low-speed digital n.c. and manufacturing test vdd 1.8v vddio 3.3v analog vss analog vdd 1.8v vss downloaded from: http:///
ds32506/ds32508/ds32512 120 of 130 right half 12 13 14 15 16 17 18 19 20 21 22 txn7 txp7 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. vss a txn7 txp7 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. b tvss7 jvss7 vss vss vss vdd18 vss vss vss n.c. n.c. c tvdd7 jvdd7 vss vss n.c. vss vss vss n.c. n.c. rclk3 d tvdd7 n.c. vss vss vss vss vss n.c. n.c. tneg7 rneg3 e tvss7 n.c. vss n.c. vss n.c. n.c. n.c. n.c. n.c. n.c. f vss n.c. vss n.c. n.c. n.c. n.c. rclk7 tpos7 tclk7 n.c. g n.c. n.c. n.c. n.c. n.c. rpos7 rneg7 n.c. rpos5 tpos3 vdd18 h vss vdd33 rclk5 rpos3 tpos5 rneg5 tclk5 tneg5 n.c. rpos1 tneg1 j vss vss vdd33 n.c. rclk1 rneg1 tclk3 n.c. tneg3 n.c. n.c. k vss vss rneg4 tpos1 tclk1 rpos2 cvdd cvdd cvss mt0 refclk l vss vss n.c. tpos4 n.c. tclk4 tneg2 clkc clkd clka clkb m vss vss vdd33 rneg8 rclk8 n.c. rclk4 tpos2 vdd18 rneg2 rclk2 n n.c. vdd33 n.c. tpos8 n.c. tclk8 vss n.c. rpos6 n.c. n.c. p n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. rpos8 rclk6 tclk2 r tvss8 vss n.c. vss n.c. n.c. n.c. n.c. n.c. tclk6 n.c. t tvdd8 gpioa8 vss n.c. vss n.c. vss n.c. n.c. tpos6 rpos4 u tvss8 n.c. vss vss vss vss vss n.c. n.c. tneg6 n.c. v tvdd8 rvss8 vss vss n.c. vss vss n.c. n.c. n.c. tneg4 w tvss8 rvdd8 n.c. vss vss vss n.c. vss vss n.c. rneg6 y txn8 rxp8 n.c. n.c. n.c. n.c. vdd18 n.c. n.c. n.c. tneg8 aa txn8 rxn8 gpiob8 n.c. n.c. n.c. n.c. n.c. n.c. n.c. vss ab 12 13 14 15 16 17 18 19 20 21 22 high-speed analog low-speed analog high-speed digital low-speed digital n.c. and manufacturing test vdd 1.8v vddio 3.3v analog vss analog vdd 1.8v vss downloaded from: http:///
ds32506/ds32508/ds32512 121 of 130 figure 12-7. ds32506 pin a ssignment, hardware a nd microprocessor interfaces left half 1 2 3 4 5 6 7 8 9 10 11 a jvdd3 tvdd3 rclki mt5 n.c. rxp5 txn5 txp5 jvss5 n.c. n.c. b hw jvss3 rpd mt6 n.c. rxn5 txn5 txp5 tvdd5 n.c. n.c. c txp3 txp3 rst jad1 tclki tcc rvss5 rvdd5 tvss5 vdd18 vss d txn3 txn3 jtdi jtclk mt1 tpd tbin rmon5 tvdd5 tlbo5 vss e rxn3 rxp3 jtrst test jas1 rbin aist gpiob5 tvss5 jvdd5 vss f tais1 rmon3 tvss3 tvdd3 rvss3 jtdo jas0 gpioa5 tvdd5 tvss5 n.c. g vdd18 gpiob1 tvss3 rvdd3 gpiob3 mt2 cladbyp jad0 tais5 vss n.c. h txp1 txp1 jvdd1 jvss1 tvss3 tais3 jtms lbs n.c. n.c. n.c. j txn1 txn1 tvdd1 tvss1 gpioa1 vss gpioa3 hiz vss vdd33 vss k rxn1 rxp1 tvss1 tvdd1 tvdd1 tvdd3 vss tlbo3 vdd33 vss vss l rvss1 resref tais2 rvdd1 vss rmon1 tlbo1 vss vss vss vss m jvdd2 jvss2 tvdd2 gpiob2 tvss2 tvdd2 gpioa2 tvss1 tlbo2 vss vss n txp2 txp2 tvdd2 tvss2 tlbo4 gpioa4 tvdd4 d11 vdd33 vss vss p txn2 txn2 rvdd2 tvss2 rvss2 tvss4 d7/cpol d13 a5 vdd33 tvdd6 r rxp2 rxn2 tais4 rmon2 d2/sclk d3 d5 d15 a3 a9 rd/ds t gpiob4 vdd18 jvss4 jvdd4 d0/sdo d1/sdi d4 a1 a7 ale n.c. u txp4 txp4 tvss4 tvdd4 d8 vss vss rdy/ ack ifsel0 tvss6 gpioa6 v tvss4 tvdd4 rvdd4 d6/cpha a0 wr/ r/ w tvdd6 tvss6 tvss6 rmon6 vss w txn4 txn4 rvss4 d9 a2 n.c. ifsel2 tais6 vss rvss6 vss y rxp4 rxn4 d10 a4 cs ifsel1 tlbo6 tvdd6 rvdd6 gpiob6 vss aa rmon4 d12 a6 mt3 n.c. jvdd6 txp6 txn6 rxp6 vdd18 n.c. ab d14 a8 int mt4 n.c. jvss6 txp6 txn6 rxn6 n.c. n.c. 1 2 3 4 5 6 7 8 9 10 11 high-speed analog low-speed analog high-speed digital low-speed digital n.c. and manufacturing test vdd 1.8v vddio 3.3v analog vss analog vdd 1.8v vss downloaded from: http:///
ds32506/ds32508/ds32512 122 of 130 right half 12 13 14 15 16 17 18 19 20 21 22 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. vss a n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. b vss vss vss vss vss vdd18 vss vss vss n.c. toe5 c vss vss vss vss n.c. vss vss vss n.c. n.c. rclk3 d vss n.c. vss vss vss vss vss n.c. n.c. n.c. rneg3 e vss n.c. vss n.c. vss n.c. n.c. n.c. n.c. n.c. rlos3 f vss n.c. vss n.c. n.c. n.c. n.c. n.c. n.c. n.c. toe3 g n.c. n.c. n.c. n.c. n.c. n.c. n.c. rlos5 rpos5 tpos3 vdd18 h vss vdd33 rclk5 rpos3 tpos5 rneg5 tclk5 tneg5 tdm5 rpos1 tneg1 j vss vss vdd33 tdm3 rclk1 rneg1 tclk3 rlos1 tneg3 tdm1 toe1 k vss vss rneg4 tpos1 tclk1 rpos2 cvdd cvdd cvss mt0 refclk l vss vss rlos6 tpos4 toe4 tclk4 tneg2 clkc clkd clka clkb m vss vss vdd33 n.c. n.c. tdm6 rclk4 tpos2 vdd18 rneg2 rclk2 n n.c. vdd33 n.c. n.c. n.c. n.c. vss tdm4 rpos6 tdm2 rlos2 p n.c. n.c. n.c. n.c. n.c. n.c. n.c. toe6 n.c. rclk6 tclk2 r vss vss n.c. vss n.c. n.c. n.c. n.c. n.c. tclk6 toe2 t vss n.c. vss n.c. vss n.c. vss n.c. n.c. tpos6 rpos4 u vss n.c. vss vss vss vss vss n.c. n.c. tneg6 rlos4 v vss vss vss vss n.c. vss vss n.c. n.c. n.c. tneg4 w vss vss n.c. vss vss vss n.c. vss vss n.c. rneg6 y n.c. n.c. n.c. n.c. n.c. n.c. vdd18 n.c. n.c. n.c. n.c. aa n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. vss ab 12 13 14 15 16 17 18 19 20 21 22 high-speed analog low-speed analog high-speed digital low-speed digital n.c. and manufacturing test vdd 1.8v vddio 3.3v analog vss analog vdd 1.8v vss downloaded from: http:///
ds32506/ds32508/ds32512 123 of 130 figure 12-8. ds32506 pin assignmen t, hardware interface only left half 1 2 3 4 5 6 7 8 9 10 11 a jvdd3 tvdd3 rclki mt5 n.c. rxp5 txn5 txp5 jvss5 n.c. n.c. b hw jvss3 rpd mt6 n.c. rxn5 txn5 txp5 tvdd5 n.c. n.c. c txp3 txp3 rst jad1 tclki tcc rvss5 rvdd5 tvss5 vdd18 vss d txn3 txn3 jtdi jtclk mt1 tpd tbin rmon5 tvdd5 tlbo5 vss e rxn3 rxp3 jtrst test jas1 rbin aist lm5[0] tvss5 jvdd5 vss f tais1 rmon3 tvss3 tvdd3 rvss3 jtdo jas0 lm5[1] tvdd5 tvss5 n.c. g vdd18 lm1[0] tvss3 rvdd3 lm3[0] mt2 cladbyp jad0 tais5 vss n.c. h txp1 txp1 jvdd1 jvss1 tvss3 tais3 jtms lbs n.c. n.c. n.c. j txn1 txn1 tvdd1 tvss1 lm1[1] vss lm3[1] hiz vss vdd33 vss k rxn1 rxp1 tvss1 tvdd1 tvdd1 tvdd3 vss tlbo3 vdd33 vss vss l rvss1 resref tais2 rvdd1 vss rmon1 tlbo1 vss vss vss vss m jvdd2 jvss2 tvdd2 lm2[0] tvss2 tvdd2 lm2[1] tvss1 tlbo2 vss vss n txp2 txp2 tvdd2 tvss2 tlbo4 lm4[1] tvdd4 n.c. vdd33 vss vss p txn2 txn2 rvdd2 tvss2 rvss2 tvss4 n.c. lb2[1] n.c. vdd33 tvdd6 r rxp2 rxn2 tais4 rmon2 lb3[0] lb4[0] lb6[0] lb4[1] vss itre n.c. t lm4[0] vdd18 jvss4 jvdd4 lb1[0] lb2[0] lb5[0] lb5[1] n.c. n.c. n.c. u txp4 txp4 tvss4 tvdd4 n.c. vss vss n.c. ifsel0 tvss6 lm6[1] v tvss4 tvdd4 rvdd4 vss n.c. n.c. tvdd6 tvss6 tvss6 rmon6 vss w txn4 txn4 rvss4 n.c. lb6[1] n.c. ifsel2 tais6 vss vss vss y rxp4 rxn4 n.c. n.c. n.c. ifsel1 tlbo6 tvdd6 rvdd6 lm6[0] vss aa rmon4 lb1[1] n.c. mt3 n.c. jvdd6 txp6 txn6 rxp6 vdd18 n.c. ab lb3[1] n.c. n.c. mt4 n.c. jvss6 txp6 txn6 rxn6 n.c. n.c. 1 2 3 4 5 6 7 8 9 10 11 high-speed analog low-speed analog high-speed digital low-speed digital n.c. and manufacturing test vdd 1.8v vddio 3.3v analog vss analog vdd 1.8v vss downloaded from: http:///
ds32506/ds32508/ds32512 124 of 130 right half 12 13 14 15 16 17 18 19 20 21 22 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. vss a n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. b vss vss vss vss vss vdd18 vss vss vss n.c. toe5 c vss vss vss vss n.c. vss vss vss n.c. n.c. rclk3 d vss n.c. vss vss vss vss vss n.c. n.c. n.c. rneg3 e vss n.c. vss n.c. vss n.c. n.c. n.c. n.c. n.c. rlos3 f vss n.c. vss n.c. n.c. n.c. n.c. n.c. n.c. n.c. toe3 g n.c. n.c. n.c. n.c. n.c. n.c. n.c. rlos5 rpos5 tpos3 vdd18 h vss vdd33 rclk5 rpos3 tpos5 rneg5 tclk5 tneg5 tdm5 rpos1 tneg1 j vss vss vdd33 tdm3 rclk1 rneg1 tclk3 rlos1 tneg3 tdm1 toe1 k vss vss rneg4 tpos1 tclk1 rpos2 cvdd cvdd cvss mt0 refclk l vss vss rlos6 tpos4 toe4 tclk4 tneg2 clkc clkd clka clkb m vss vss vdd33 n.c. n.c. tdm6 rclk4 tpos2 vdd18 rneg2 rclk2 n n.c. vdd33 n.c. n.c. n.c. n.c. vss tdm4 rpos6 tdm2 rlos2 p n.c. n.c. n.c. n.c. n.c. n.c. n.c. toe6 n.c. rclk6 tclk2 r vss vss n.c. vss n.c. n.c. n.c. n.c. n.c. tclk6 toe2 t vss n.c. vss n.c. vss n.c. vss n.c. n.c. tpos6 rpos4 u vss n.c. vss vss vss vss vss n.c. n.c. tneg6 rlos4 v vss vss vss vss n.c. vss vss n.c. n.c. n.c. tneg4 w vss vss n.c. vss vss vss n.c. vss vss n.c. rneg6 y n.c. n.c. n.c. n.c. n.c. n.c. vdd18 n.c. n.c. n.c. n.c. aa n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. vss ab 12 13 14 15 16 17 18 19 20 21 22 high-speed analog low-speed analog high-speed digital low-speed digital n.c. and manufacturing test vdd 1.8v vddio 3.3v analog vss analog vdd 1.8v vss downloaded from: http:///
ds32506/ds32508/ds32512 125 of 130 figure 12-9. ds32506 pin assignment, microprocessor interface only left half 1 2 3 4 5 6 7 8 9 10 11 a jvdd3 tvdd3 n.c. mt5 n.c. rxp5 txn5 txp5 jvss5 n.c. n.c. b hw jvss3 n.c. mt6 n.c. rxn5 txn5 txp5 tvdd5 n.c. n.c. c txp3 txp3 rst n.c. n.c. n.c. rvss5 rvdd5 tvss5 vdd18 vss d txn3 txn3 jtdi jtclk mt1 n.c. n.c. n.c. tvdd5 n.c. vss e rxn3 rxp3 jtrst test n.c. n.c. n.c. gpiob5 tvss5 jvdd5 vss f n.c. n.c. tvss3 tvdd3 rvss3 jtdo n.c. gpioa5 tvdd5 tvss5 n.c. g vdd18 gpiob1 tvss3 rvdd3 gpiob3 mt2 cladbyp n.c. n.c. vss n.c. h txp1 txp1 jvdd1 jvss1 tvss3 n.c. jtms n.c. n.c. n.c. n.c. j txn1 txn1 tvdd1 tvss1 gpioa1 vss gpioa3 hiz vss vdd33 vss k rxn1 rxp1 tvss1 tvdd1 tvdd1 tvdd3 vss n.c. vdd33 vss vss l rvss1 resref n.c. rvdd1 vss n.c. n.c. vss vss vss vss m jvdd2 jvss2 tvdd2 gpiob2 tvss2 tvdd2 gpioa2 tvss1 n.c. vss vss n txp2 txp2 tvdd2 tvss2 n.c. gpioa4 tvdd4 d11 vdd33 vss vss p txn2 txn2 rvdd2 tvss2 rvss2 tvss4 d7/cpol d13 a5 vdd33 tvdd6 r rxp2 rxn2 n.c. n.c. d2/sclk d3 d5 d15 a3 a9 rd/ds t gpiob4 vdd18 jvss4 jvdd4 d0/sdo d1/sdi d4 a1 a7 ale n.c. u txp4 txp4 tvss4 tvdd4 d8 vss vss rdy/ ack ifsel0 tvss6 gpioa6 v tvss4 tvdd4 rvdd4 d6/cpha a0 wr/ r/ w tvdd6 tvss6 tvss6 n.c. vss w txn4 txn4 rvss4 d9 a2 n.c. ifsel2 n.c. vss rvss6 vss y rxp4 rxn4 d10 a4 cs ifsel1 n.c. tvdd6 rvdd6 gpiob6 vss aa n.c. d12 a6 mt3 n.c. jvdd6 txp6 txn6 rxp6 vdd18 n.c. ab d14 a8 int mt4 n.c. jvss6 txp6 txn6 rxn6 n.c. n.c. 1 2 3 4 5 6 7 8 9 10 11 high-speed analog low-speed analog high-speed digital low-speed digital n.c. and manufacturing test vdd 1.8v vddio 3.3v analog vss analog vdd 1.8v vss downloaded from: http:///
ds32506/ds32508/ds32512 126 of 130 right half 12 13 14 15 16 17 18 19 20 21 22 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. vss a n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. b vss vss vss vss vss vdd18 vss vss vss n.c. n.c. c vss vss vss vss n.c. vss vss vss n.c. n.c. rclk3 d vss n.c. vss vss vss vss vss n.c. n.c. n.c. rneg3 e vss n.c. vss n.c. vss n.c. n.c. n.c. n.c. n.c. n.c. f vss n.c. vss n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. g n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. rpos5 tpos3 vdd18 h vss vdd33 rclk5 rpos3 tpos5 rneg5 tclk5 tneg5 n.c. rpos1 tneg1 j vss vss vdd33 n.c. rclk1 rneg1 tclk3 n.c. tneg3 n.c. n.c. k vss vss rneg4 tpos1 tclk1 rpos2 cvdd cvdd cvss mt0 refclk l vss vss n.c. tpos4 n.c. tclk4 tneg2 clkc clkd clka clkb m vss vss vdd33 n.c. n.c. n.c. rclk4 tpos2 vdd18 rneg2 rclk2 n n.c. vdd33 n.c. n.c. n.c. n.c. vss n.c. rpos6 n.c. n.c. p n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. rclk6 tclk2 r vss vss n.c. vss n.c. n.c. n.c. n.c. n.c. tclk6 n.c. t vss n.c. vss n.c. vss n.c. vss n.c. n.c. tpos6 rpos4 u vss n.c. vss vss vss vss vss n.c. n.c. tneg6 n.c. v vss vss vss vss n.c. vss vss n.c. n.c. n.c. tneg4 w vss vss n.c. vss vss vss n.c. vss vss n.c. rneg6 y n.c. n.c. n.c. n.c. n.c. n.c. vdd18 n.c. n.c. n.c. n.c. aa n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. vss ab 12 13 14 15 16 17 18 19 20 21 22 high-speed analog low-speed analog high-speed digital low-speed digital n.c. and manufacturing test vdd 1.8v vddio 3.3v analog vss analog vdd 1.8v vss downloaded from: http:///
ds32506/ds32508/ds32512 127 of 130 13. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. the package number provided for each package is a link to the latest package outline information.) 13.1 484-lead bga (23mm x 23mm) ( 56-g60038-001 ) downloaded from: http:///
ds32506/ds32508/ds32512 128 of 130 14. thermal information table 14-1. thermal propert ies, natural convection parameter min typ max units ambient temperature (note 1) -40 +85 c junction temperature -40 +125 c theta - ja ( ja ), still air (note 1) 16.0 c/w theta-jc ( jc ) 5.4 c/w psi-jb 7.7 c/w psi-jt 0.4 c/w note 1: the package is mounted on a four - layer jedec standard test board with no airflow and dissipating maximum power. table 14-2. theta-ja ( ja ) vs. airflow forced air (meters per second) theta-ja ( ja ) 0 16.0 c/w 1 13.8 c/w 2 12.8 c/w downloaded from: http:///
ds32506/ds32508/ds32512 129 of 130 15. acronyms a nd abbreviations ais alarm indication signal ami alternate mark inversion b3zs bipolar with three-zero substitution ber bit-error rate, bit-error ratio bpv bipolar violation cv code violation ds3 digital signal, level 3 exz excessive zeros hdb3 high-density bipolar of order 3 io, i/o input/output liu line interface unit lol loss of lock los loss of signal lsb least significant bit msb most significant bit pdh plesiochronous digital hierarchy prbs pseudo-random bit sequence rx, rx receive sonet synchronous optical network sdh synchronous digital hierarchy sts synchronous transmission signal sts-1 synchronous transmission signal at level 1 tx, tx transmit ui unit interval ui p-p unit interval peak-to-peak ui rms unit intervals root mean square 16. trademark acknowledgements accunet is a registered trademark of at&t. spi is a trademark of motorola, inc. telcordia is a registered trademark of telcordia technologies. downloaded from: http:///
ds32506/ds32508/ds32512 130 of 130 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2008 maxim integrated products the maxim logo is a registered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. 17. data sheet re vision history revision date description pages changed 062906 initial data sheet release. added internal receive enable (itre) pin to table 7-1 . short pin descriptions. 14 changed vdd18 tolerance from 10% to 5% ( table 7-1 . short pin descriptions). 15 added internal receive enable (itre) pin description to table 7-5 . hardware interface pin description. 20 changed vdd18 tolerance from 10% to 5% ( table 7-10 . power-supply pin descriptions). 23 in section 8.2.8 , removed note that internal termination is only available when a microprocessor interface is enabled. 25 changed rxp to txn in the third paragraph of section 8.2.9: driver monitor and output failure detection . 26 in section 8.3.1 , removed note that internal termination is only available when a microprocessor interface is enabled. 30 removed section 8.12: initialization . 48 in the absolute maximum ratings section, changed the vdd18 supply range from -0.1v to +1.98v to -0.1v to +1.89v. in table 11-1 , changed vdd18 from 1.62v (min) to 1.71v (min) and 1.98v (max) to 1.89v (max). 92 in table 11-2 , changed all i dd18 , i dd33 , i ddtts18 , and i ddtts33 typ and max values. 93 in table 11-2 to table 11-10 , changed vdd18 tolerance from 10% to 5%. 93, 94, 96, 97, 98, 103, 105 in table 12-1 , added itre to ball r10. 106 091307 in figure 12-2 , figure 12-5 , and figure 12-8 , changed ball r10 from n.c. to itre for ds32512, ds32508, and ds32506 hardware-interface-only pin assignments. 111, 117, 123 040808 in figure 12-8 (left half), corrected typos where some pins for port 7 were listed (do not exist on the ds32506). changed pins a10, a11, b10, b11, f11, and g11 to n.c. changed pins c11, d11, e11, g10, r9, and v4 to vss. 123 103008 in section 9.7 , clarified register bit text descriptions for line.rsr :bpvc and line.rsr :excz. 83 downloaded from: http:///

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